Tutorial:Synopsys Core Tools Tutorial

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Introduction

This tutorial will introduce you to the Synopsys Core Tools, which are used to configure and synthesize Synopsys' Design Ware System-Level IP cores, including AMBA buses and memory controllers. This tutorial is not indented to take you through the different core options and how best to assemble them into a working system. Rather, it is intended only to familiarize you with the user interface so that you can do your own exploration.

Start the Core Consultant GUI

Login to an Eos Linux Lab Machine, and change to the directory where you want to run the tutorial. Then set up your environment with the following commands:

add synopsys_new
source /afs/eos.ncsu.edu/lockers/research/ece/wdavis/tools/synopsys/core_tools_setup.csh
coreConsultant

You should see the coreConsultant startup screen appear, as shown below.

CoreConsultant startup.png

Configure the DW_ahb Component

Click on the DW_ahb component. You will be prompted to type the name for the workspace for this configuration of the DW_ahb component. The default is set to a subdirectory named i_ahb in the current working directory.

After selecting the directory, you will see the coreConsultant window updated as shown below. The Activity List pane is now filled in with all of the steps that need to be completed in order to generate a synthesizable netlist for this component. Once complete, the step will have a check-mark next to it.

CoreConsultant specifyconfig.png

Click Next to step through all of the pages and all of the configuration parameters that you can set. Use the default parameters, 2 masters and 4 slaves. Once you have scanned all of the options, click Apply. coreConsultant will create the i_ahb directory and elaborate the component.

Create the Gate-Level Netlist

Click on the Activity Specify Target Technology under the Create Gate-Level Netlist heading. Add the following entries by clicking the Insert New Item button in the upper-right of each section (looks like a little white square with a yellow star in the corner).

Section Text to add
search_path /afs/eos.ncsu.edu/lockers/research/ece/wdavis/tech/nangate/NangateOpenCellLibrary_PDKv1_3_v2010_12/Front_End/Liberty/CCS
target_library NangateOpenCellLibrary_typical_ccs.db
link_library NangateOpenCellLibrary_typical_ccs.db
link_library dw_foundation.sldb

Click Apply.

Next, click the Perform ASIC Synthesis Activity. You will be asked if you want to automatically complete all dependent activities. Click Yes. Set the Strategy to DCTCL_opto_strategy (which should be the default). Then click Apply.

Synthesis will take several minutes to complete. Once finished, the final netlist will be in the file i_ahb/syn/final/db/DW_ahb.v. You can also find synthesis reports in the directory i_ahb/syn/incr#/report (where incremental synthesis runs are indexed as incr1, incr2, and so on). Perhaps the most useful reports are called DW_ahb_area.rpt and DW_ahb_timing.rpt.

For more information

For more information on Design Ware AMBA IP Cores and how to configure them, see the documentation that comes with each core. These can be found in the following AFS directory:

/afs/eos.ncsu.edu/lockers/research/ece/wdavis/tools/synopsys/DW_AMBA/iip/CORENAME/latest/doc

Note also that the DW_ahb core has a great tutorial in its documentation directory, in a file named dw_ahb_tt.pdf. This file takes you through an example that uses and AHB bus, memory controller, interrupt controller, and APB bridge.