Tutorial:Questa SystemC Tutorial

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INTRODUCTION

This tutorial deals with the provision of a typical SystemC code structure and its simulation using Questa/Modelsim from Mentor Graphics

Tutorial: SystemC: Introduction, Simulation using Questa/Modelsim and Transaction Level Models

The tutorial can be downloaded at: pdf doc (last modified July 7, 2008)

The aim of this tutorial is to understand the basic language constructs of SystemC. These language fundamentals are going to be used in the description of a simple FIR filter design. The FIR filter consists of a producer that generates data that is needed as an input and an accelerator that computes the FIR result. The two units communicate with each other over nets and also share common input signals for clock, reset and enable. Additionally, we will provide an example of a Transaction Level Model (TLM) of the above system. This is done by introducing the need for a FIFO between the accelerator and the producer to deal with issues of the sub-modules working at different rates. This connectivity is achieved by the use of a sc_fifo transaction level channel and its interfaces.

The necessary files for this tutorial

FILES FOR PART 1

Please download as directed in the tutorial

VSIM#> do compile.do

FILES FOR PART 2

Please download as directed in the tutorial