Layout Tutorial #3
In this tutorial you will create the layout for a hierarchical, sequential circuit, extract it, and simulate it with SPICE.
Create a new cell
Start by creating a cell called “tut3”. Create a new schematic view. The circuit that we will create is shown below. It contains 7 instances of 2 different standard cells from a library called tut3cells. In order to see this library, add the following line to the cds.lib file in the directory where you started Cadence (should be a single line):
DEFINE tut3cells /afs/eos.ncsu.edu/lockers/research/ece/wdavis/tech/ece546/tut3cells
Next choose View->Refresh in the library manager window. You should see the tut3cells library appear. NOTE: If you examine these layouts, you will see that they are not very dense. It is suggested that you try to make denser layouts, so that your designs will have shorter wires.
Next, create instances of the flip-flop and XOR from the drawing above. Choose Create->Instance in the schematic editor window, or press the “I” key. Click Browse and select the tut3cells library. You should see all of the cells in the library. Add 5 instances of "DFFPOSX1" "symbol" and 2 instances of "XOR2X1" "symbol". Wire the schematic as shown above. Be sure also to add a CLK input pin, and connect it to the flip-flop clocks. Create wire labels with Create -> Wire Name, or press the "L" key. Be sure to follow the instance names (i0 ... i5) and net names (n0 ... n6) above, to avoid confusion later on in the tutorial.
For your project, it is suggested that you break your design up into units, like these standard-cells, and that you create symbols to refer to these units. In this lab, the symbols are provided for you, but you could have just as easily made them yourself. Start with a completed schematic and choose Design->Create CellView->From CellView… and give the schematic as input.
Next, create a layout view. Create instances of the flip-flop and XOR from the drawing above. Choose Create->Instance in the layout editor window, or press the “I” key. Click “Browse” in the pop-up window and click on the “tut3cells” “DFFPOSX1” “layout” cell. Click in the layout to place one instance. Then browse again for the “XOR2X1” “layout” cell. Add one instance of that as well. Click “Cancel” to stop adding instances.
Next, zoom out (by pressing “Shift-Z”) and copy the D flip-flop 4 times by selecting Edit->Copy in the layout editor window, or press the “C” key. Click on the instance and click elsewhere to place the copy. Also copy the XOR gate once. Click “Cancel” to stop copying instances.
Next arrange the instances so that they appear as in the figure below. Note that the origin is in the lower, left-hand corner. By convention, we usually put the origin in the lower, left-hand corner of our layout. The images below show what you see with (left) and without (right) hierarchy expanded.
Note that the cells in this library are all exactly the same height, have power and ground rails of exactly the same width, and have n-wells with the same Y-dimension. This is necessary to ensure that there are no design-rule violations when tiling them.
Compact the layout
Now, let’s compact the layout so that we use as little area as possible. You’ll notice that the top rail is VDD and the bottom rail is GND for each cell. In order to compact them optimally, we’ll have to flip the cells on row 2. Select each one of these cells and select File->Properties… (or hit “Q”). Under the “attribute” heading, set the “rotation” to “MX”, which stands for “mirrored on the X-axis”. Now compact the layout until it looks like the one below.
Next, select Calibre->Run DRC to make sure that you have no DRC errors. If you have DRC errors, then it’s possible that you haven’t compacted enough. One way to tell if you have tiled the cells correctly is to look at the “prBoundary” shapes (which stands for “Place-and-Route Boundary”). Make sure that the “prBoundary” “drawing” layer is visible in the LSW and make all other layers invisible. (You may need to make this layer valid with Edit->Set Valid Layers… in the LSW before you can make it visible). When tiled correctly, you should see all of the “prBoundary” shapes touching, with no space between them, as shown below.
Connect supply rails
Next, we need to connect the supply rails so that VDD and GND are each a single net in the extracted view. Connect the power with a metal1 path as shown below and create the labels “vdd!” and “gnd!” for these nets.
Connect signal nets
Next, we need to connect the cells as shown in the figure on the first page. Look for the labels in the layout view in order to figure out which pin in each standard-cell should be connected to which net in the design.
Connect the layout as shown in the schematic above. While connecting different layers together, you need to use proper vias. The various types of vias available are as follows:
- M1_N : For N-well to Metal1 connection
- M1_P : For P-well to Metal1 connection
- NTAP : For N-well to VDD connection
- PTAP : For P-well to VDD connection
- M1_POLY : For Poly (Gate of transistor) to Metal1 connection
- M2_M1 : For Metal2 to Metal1 Connection
- M3_M2 : Metal3 to Metal2 connection
- M4_M3 : Metal4 to Metal3 connection
- M5_M4 : Metal5 to Metal4 connection
- M6_M5 : Metal6 to Metal5 connection
- M7_M6 : Metal7 to Metal6 connection
- M8_M7 : Metal8 to Metal7 connection
- M9_M8 : Metal9 to Metal8 connection
- M10_M9 : Metal10 to Metal9 connection
As you should notice, the vias are available for connecting one metal layer to the next higher layer. So if you need to connect Metal1 to Metal3 then you need to place both M2_M1 contact and M3_M2 contact together.
You should be very careful while placing contacts. Incorrect contacts can short two nets and result in LVS Error.
Create pins for all of the inputs and outputs (A<0>, A<1>, A<2>, B<0>, B<1>). Be sure also to add a clock node (called CLK) and connect all of the clock inputs. Do NOT create labels for the interior nodes (n0, … , n4). Doing so would cause these nodes to be interpreted as ports by Calibre, causing you to fail the LVS check. When you are done, the layout should look like the one below. Notice that this figure shows only metals 1, 2, and 3, but you’re free to use as many (or as few) layers as you wish.
Perform an LVS check to make sure that your layout matches your schematic. You may find that you had a number of errors that you need to fix. This process becomes increasingly difficult as the layout gets larger. What’s more, if you don’t trust the layout of the standard-cells to be correct, then this process is nearly impossible. Therefore, it is strongly suggested that you use hierarchy as your layout increases in complexity, performing LVS checks at each level to make sure that everything is correct.
Now extract the parasitics with Calibre and create an HSPICE netlist. Use the "C+CC" option to keep the netlist small.
Open the netlist you just created. You should notice that it includes all capacitances and that it contains one top-level subcircuit definition, named TUT3.
Create a new file called tut3.sp. Set it up to perform a transient simulation that lasts 4ns. Next, include the file TUT3.pex.netlist and create an instance of the top-level subcircuit in that file. You'll need to follow the port-order in your particular TUT3.pex.netlist file, but in my case, the lines I add look like this:
.include 'TUT3.pex.netlist' X0 vdd! 0 clk b<0> a<0> a<1> b<1> a<2> tut3
Next, add the following sources:
Vclk CLK 0 PULSE 0 1.0 0 20p 20p 180p 400p Vdd VDD! 0 1.0
The first is a clock source, with a 400ps period, and 20ps rise and fall times. The second is the supply voltage. The only thing that remains is input patterns for A<0>, A<1>, and A<2>. To implement these signals, add the following line…
…and then create a text file called tut3.dat in the directory where you will run HSPICE. Cut-and-paste the contents of the box below to put into this file. You'll notice from the comments below that this file defines input patterns for all of your signals in a very convenient format.
; Digital input pattern for HSPICE ; ";" is a flag for comments line ; ; To use this digital input pattern, in your Hspice netlist, ; add one line: .VEC 'vectors.dat' ; Don't connect any voltage source to the pin/terminal which ; you want to feed with this digital stream. ; ; This file can be used for any system-level simulation. ; Just modify the patterns below. ; ; For more information, see the section title "Specifying ; a Digital Vector File" in the HSPICE Simulation and ; Analysis User Guide (linked from the HSPICE "documentation ; page" link on the course web-page, under "tool tips") ; ; Define the radix for each pin (1 for each pin) radix 1 1 1 ; List the pin names vname A<0> A<1> A<2> ; Define pin I/O (i for each pin) io i i i ; Define time unit (ns in this example) tunit ns ; Define slope of signal edge (20 ps rising/falling ; time in this example) slope 0.02 ; Define high voltage (1.8V) vih 1.0 ; Define low voltage (0V) vil 0.0 ; Define the delay for the first instruction ; (100 ps in this example, to shift away from the clock edge) tdelay 0.2 ; Define the period for the vectors (500 ps in this example) period 0.4 ; ; The following are the vectors ; A<0> A<1> A<2> ; 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1
Run the HSPICE simulation. You should see waveforms like the ones below.
Critical Path Simulation
The waveforms above demonstrate the circuit’s functionality, but they do not necessarily demonstrate the critical-path delay. We need a set of vectors that demonstrates the critical-path so that we can measure its delay in HSPICE. In addition, we'd like to use "R + C + CC" extraction, so that we get the best idea of the delay introduced by the wire resistances.
Unfortunately, setting up this critical-path simulation can be difficult, because the netlists can get very large, complex, and slow to simulate. We can simplify things by recognizing that we don't need to include every node in the simulation. All we need are the nodes in the critical-path, which most-likely includes the nodes n0 or n1, n3, and n4, plus the flip-flops and XOR gates connected to those nodes. We'll also need to have nodes A<0>, A<1>, and CLK so that we can properly drive the flip-flops, and node B<1> so that we can properly check if it's working. For the other nodes (such as n2), we'll need to sensitize the path, which means that we need to choose some constant value that allows node n4 to change whenever n3 changes. But we don't need parasitic information for n2.
To extract parasitics for the nodes of interest, return to the Calibre Interactive - PEX window, and change the options as follows:
- Under Inputs -> Layout, deselect Export from layout viewer. Assuming that you already have already run PEX once, the gds file in the directory should be up-to-date and doesn't need to be exported again.
- Likewise, deselect Export from schematic viewer under Inputs -> Netlist
- Under Outputs, change the extraction type to R + C + CC
- Under Outputs -> Nets, select Extract parasitics for: Specified Nets. The click the Top-Level Nets tab, select Include and enter the following net names in the box to the right (all on one line):
A<0> A<1> CLK n0 n1 n3 n4 B<1> Xi0/CLKB Xi0/n1 Xi0/n2 Xi0/n3 Xi0/n4 Xi0/n5 Xi0/n6 Xi0/n7 Xi0/n8 Xi0/n9 Xi0/n10 Xi0/n11 Xi1/CLKB Xi1/n1 Xi1/n2 Xi1/n3 Xi1/n4 Xi1/n5 Xi1/n6 Xi1/n7 Xi1/n8 Xi1/n9 Xi1/n10 Xi1/n11 Xi6/CLKB Xi6/n1 Xi6/n2 Xi6/n3 Xi6/n4 Xi6/n5 Xi6/n6 Xi6/n7 Xi6/n8 Xi6/n9 Xi6/n10 Xi6/n11 Xi3/bn Xi3/n1 Xi3/n2 Xi3/i1 Xi4/bn Xi4/n1 Xi4/n2 Xi4/i1
Note that the top line above includes the top-level net names of interest. The next three lines give the internal names of the three flip-flops of interest, and the last two lines give the internal names of the XOR gates. The slash "/" is used to denote levels of hierarchy, and all internal names have the prefix "X", which follows the HSPICE naming scheme for subcircuit instances. If you get tired of cutting and pasting into the Calibre Interactive window, note that you can edit the line pexPexTopLevelIncludeNetsValue in the file .runset.calibre.pex to include the nets you want. You can then load this file with the command File -> Load Runset. Be sure to say "no" when asked if you want to save the runset, or it will overwrite the changes you just made.
If you're worried that the names you enetered may not have been recognized by Calibre, you can look for the following lines in the PEX transcript:
--- CREATING XREF INFORMATION FROM XDB DATABASE Selected nets: A<0> will be included. A<1> will be included. ...
If Calibre did not recognize one or more of the net names you specified, you will see error messages here.
One more optimization remains. When simulating large systems, it can be very inconvenient to deal with the huge amount of data that is produced. Your disk-quota can fill up very quickly, and simulations can be slowed by the amount of time needed to physically write all of the output data to disk. You can speed this up by telling HSPICE to include only the nodes of interest in the output. Do this by specifying the option PROBE before the POST option in your .OPTION statement, and then adding a .PROBE statement to list the variables that you want in your output file:
.OPTIONS ... + PROBE POST .PROBE TRAN v(a<0>) v(a<1>) v(a<2>) v(b<0>) v(b<1>) v(clk)
Note that if you want to see the internal nodes to the subcircuit X0, then you'll need to include it in the list above as "X0.nodename". The nodes will have changed names due to the parasitic extraction process, and your node names may differ from mine. But in my case, the internal node n0 has been mapped to 8 different nodes in the extracted netlist, one of which is named "N_n0_XI0/MM22_g". Look in your own TUT3.pex.netlist file to find out how your node names have been mapped. So, if I wanted to include this internal node in my .PROBE list, I would write it as
.PROBE TRAN v(X0.N_n0_XI0/MM22_g)
Make these changes now to simulate the critical-path of this design. Suggest a set of vectors that sensitize the critical-path and measure its delay. Assume that the critical-path starts at node CLK (meaning that it will include the CLK-Q delay) and ends at node n4. Be sure to include a mix of rising and falling transitions to verify that you're actually measuring the longest delay.