Tutorial:CDK Layout Tutorial 3
Layout Tutorial #3
In this tutorial you will create the layout for a hierarchical, sequential circuit, extract it, and simulate it with SPICE, NanoSim and PathMill.
Create a new cell
Start by creating a cell called “tut3”. Create a new schematic view. The circuit that we will create is shown below. It contains 7 instances of 2 different standard cells from the IIT standard-cell library. In order to see this standard-cell library, add the following line to the cds.lib file in the directory where you started Cadence (should be a single line):
DEFINE IIT_stdcells_tsmc018 /afs/eos.ncsu.edu/lockers/research/ece/wdavis/tech/iit/iit_stdcells/tsmc018/IIT_stdcells_tsmc018
Next choose View->Refresh in the library manager window. You should see the IIT_stdcells_tsmc018 library appear.
Next, create instances of the flip-flop and XOR from the drawing above. Choose Create->Instance in the layout editor window, or press the “I” key. Select the IIT_stdcell_tsmc018 library in the component-browser, and click on “Uncategorized”. You should see all of the cells in the library. Add 5 instances of “DFFPOSX1” and 2 instances of “XOR2X1”. Wire the schematic as shown above. Be sure also to add a CLK input pin, and connect it to the flip-flop clocks.
For your project, it is suggested that you break your design up into units, like these standard-cells, and that you create symbols to refer to these units. In this lab, the symbols are provided for you, but you could have just as easily made them yourself. Start with a completed schematic and choose Design->Create CellView->From CellView… and give the schematic as input.
Next, create a layout view. Create instances of the flip-flop and XOR from the drawing above. Choose Create->Instance in the layout editor window, or press the “I” key. Click “Browse” in the pop-up window and click on the “IIT_stdcells_tsmc018” “DFFPOSX1” “layout” cell. Click in the layout to place one instance. Then browse again for the “XOR2X1” “layout” cell. Add one instance of that as well. Click “Cancel” to stop adding instances.
Next, zoom out (by pressing “Shift-Z”) and copy the D flip-flop 4 times by selecting Edit->Copy in the layout editor window, or press the “C” key. Click on the instance and click elsewhere to place the copy. Also copy the XOR gate once. Click “Cancel” to stop copying instances.
Next arrange the instances so that they appear as in the figure below. Note that the origin is in the lower, left-hand corner. By convention, we usually put the origin in the lower, left-hand corner of our layout. The images below show what you see with (left) and without (right) hierarchy expanded.
Note that the cells in this library are all exactly the same height, have power and ground rails of exactly the same width, and have n-wells with the same Y-dimension. This is necessary to ensure that there are no design-rule violations when tiling them.
Compact the layout
Now, let’s compact the layout so that we use as little area as possible. You’ll notice that the top rail is VDD and the bottom rail is GND for each cell. In order to compact them optimally, we’ll have to flip the cells on row 2. Select each one of these cells and select Edit->Properties… (or hit “Q”). Under the “attribute” heading, set the “rotation” to “MX”, which stands for “mirrored on the X-axis”. Now compact the layout until it looks like the one below.
Next, select Verify->DRC… to make sure that you have no DRC errors. If you have DRC errors, then it’s possible that you haven’t compacted enough. One way to tell if you have tiled the cells correctly is to look at the “prBoundary” shapes (which stands for “Place-and-Route Boundary”). Make sure that the “prBoundary” “drawing” layer is visible in the LSW and make all other layers invisible. (You may need to make this layer valid with Edit->Set Valid Layers… in the LSW before you can make it visible). When tiled correctly, you should see all of the “prBoundary” shapes touching, with no space between them, as shown below.
Connect supply rails
Next, we need to connect the supply rails so that VDD and GND are each a single net in the extracted view. Connect the power with a metal1 path as shown below and create the labels “vdd!” and “gnd!” for these nets.
Connect signal nets
Next, we need to connect the cells as shown in the figure on the first page. It isn’t easy to figure out which pin on the standard-cell corresponds to the pins in the figure, because there aren’t any labels in the layout view. In order to figure out which pin goes to which shape in the layout, open the “abstract” view for each cell. From there, you should be able to figure it out.
Connect the layout as shown in the figure on page 1. While connecting different layers together, you need to use proper contacts. The various types of contacts available are as follows:
M1_P : For P-well to Metal1 conection
M1_N : For N-well to Metal1 connection
NTAP : For N-well to VDD connection
M1_Poly : For Poly (Gate of transistor) to Metal1 connection
M2_M1 : For Metal2 to Metal1 Connection
M3_M2 : Metal3 to Metal2 connection
M4_M3 : Metal4 to Metal3 connection
M5_M4 : Metal5 to Metal4 connection
M6_M5 : Metal6 to Metal5 connection
As you can notice, the contacts are available for connecting one metal layer to the next higher layer. So if you need to connect Metal1 to Metal3 then you need to place both M2_M1 contact and M3_M2 contact together.
You should be very careful while placing contacts. Incorrect contacts can short two nets and result in LVS Error.
Create pins for all of the inputs and outputs (A<0>, A<1>, A<2>, B<0>, B<1>) and labels for the interior nodes (n0, … , n4). Be sure also to add a clock node (called CLK) and connect all of the clock inputs. When you are done, the layout should look like the one below. Notice that this figure shows only metals 1, 2, and 3, but you’re free to use as many (or as few) layers as you wish.
Perform an LVS check to make sure that your layout matches your schematic. You may find that you had a number of errors that you need to fix. This process becomes increasingly difficult as the layout gets larger. What’s more, if you don’t trust the layout of the standard-cells to be correct, then this process is nearly impossible. Therefore, it is strongly suggested that you use hierarchy as your layout increases in complexity, performing LVS checks at each level to make sure that everything is correct.
Now extract the layout and create an HSPICE netlist. Remember to use the command NCSU_parasiticCapIgnoreThreshold = 0 in order to get the wire capacitances.
Open the netlist you just created. You should notice that the names have been changed slightly. First of all, the nodes names “n0”, “n1”, etc. have been mapped to “N0”, “N1”, etc. Note also that the nodes named “A<0>”, “A<1>”, etc. have been mapped to A_0, A_1, etc. It’s important to remember these new names, so that you can create a set of input patterns that use these names.
Edit your netlist. Set it up to perform a transient simulation that lasts 10ns. Add the following sources:
Vclk CLK 0 PULSE 0 1.8 0 100p 100p 500p 1n Vdd VDD! 0 1.8
The first is a clock source, with a 1ns period, and 100ps rise and fall times. The second is the supply voltage. The only thing that remains is input patterns for A_0, A_1, and A_2. To implement these signals, add the following line…
…and then create a text file called tut3.dat in the directory where you will run HSPICE. Cut-and-paste the contents of the box below to put into this file. You'll notice from the comments below that this file defines input patterns for all of your signals in a very convenient format.
; Digital input pattern for HSPICE ; ";" is a flag for comments line ; ; To use this digital input pattern, in your Hspice netlist, ; add one line: .VEC 'vectors.dat' ; Don't connect any voltage source to the pin/terminal which ; you want to feed with this digital stream. ; ; This file can be used for any system-level simulation. ; Just modify the patterns below. ; ; For more information, see the section title "Specifying ; a Digital Vector File" in the HSPICE Simulation and ; Analysis User Guide (linked from the HSPICE "documentation ; page" link on the course web-page, under "tool tips") ; ; Define the radix for each pin (1 for each pin) radix 1 1 1 ; List the pin names vname A_0 A_1 A_2 ; Define pin I/O (i for each pin) io i i i ; Define time unit (ns in this example) tunit ns ; Define slope of signal edge (0.1ns rising/falling ; time in this example) slope 0.1 ; Define high voltage (1.8V) vih 1.8 ; Define low voltage (0V) vil 0.0 ; Define the delay for the first instruction ; (0.1ns in this example, to shift away from the clock edge) tdelay 0.1 ; The first column is the start point for each instruction ; In this example, the period is 1 ns. ; You can change the number in first column to achieve a higer speed. ; ; The following are the vectors ; time A_0 A_1 A_2 ; 0 0 0 0 1 1 0 0 2 0 1 0 3 1 1 0 4 0 0 1 5 1 0 1 6 0 1 1 7 1 1 1
Run the HSPICE simulation. You should see waveforms like the ones on the following page.
These waveforms demonstrate the circuit’s functionality, but they do not necessarily demonstrate the critical-path delay. Suggest a set of vectors that demonstrate the critical-path delay and measure this delay using HSPICE.