Tutorial:CDK Layout Tutorial 2
Layout Tutorial #2: Extraction and LVS
In this tutorial you will create the schematic and layout for a NAND gate, and then perform a layout-vs.-schematic (LVS) check to verify the connectivity. You’ll also perform a parasitic extraction and generate an HSPICE netlist with accurate wire- and source-/drain- capacitances generated from the layout.
Note that some of the images in this tutorial have been reduced for readability. To see the full-size image, click twice on the image.
Create the NAND2 Schematic
Create a cell called “nand2”, and make a schematic like the one shown below. Note that the all transistors (NMOS and PMOS) have a width of 600 nm. Note also that you can add a “Wire Name” to internal nodes by selecting Add->Wire Name or by hitting the “l” (lower case “L”) key. The figure shows that the node between the two NMOS transistors has been given the name “X”. When you generate an HSPICE netlist, this node will now have a more meaningful name, rather than something random like “NET41”.
Check and save the schematic.
Create the NAND2 Layout
Now create the layout view. Create an instance of an NMOS transistor. Set Width to “600n M” and Fingers to 2. Also create two instances of PMOS transistors, with their Widths set to “600n M”.
Now connect up the devices with metal1 and poly as shown below.
Next, we’ll most likely want to connect the inputs to this cell using a metal wire to another cell. Create contacts to bring the poly wires up to metal1. Select Create->Contact or hit the “o” key. Set contact type to M1_POLY, and create contacts as shown below. Click “cancel” when done. Then create the remaining poly wire to connect the contact to the gates.
Finally, add pins named vdd!, gnd!, A, B, and Z to match the layout below. (Note that the pins named A and B are on the left and right M1_POLY contacts, although it’s kind of hard to tell from the picture). Make sure that the I/O Type is set to “inputOutput” for pins vdd! and gnd!, “input” for pins A and B, and “output” for pin Z.
Extract the Layout
When you are done creating the layout, save the design, and then select Verify->Extract… . Make sure Extract Method is set to “flat”, Echo Commands is unchecked. Click Ok. You should see the following messages appear in the CIW:
Extraction started.......Mon Sep 13 19:33:07 2004 completed ....Mon Sep 13 19:33:08 2004 CPU TIME = 00:00:00 TOTAL TIME = 00:00:01 ********* Summary of rule violations for cell "nand2 layout" ********* Total errors found: 0
You should also notice that a new cell view has been created, called “extracted”. Open the extracted view and examine it. You should see something like the image below. You’ll notice that the layers in the extracted view are like the ones in the layout view (metal1, poly, etc.) except that they’re in the “net” purpose (“nt”) rather than the “drawing” purpose (“dg”). (The pin rectangles that you created, however, will still be in the “drawing” purpose). Cadence uses the different “purposes” to distinguish shapes that are meant for different things. Here, for example, the net purpose is used to indicate that the shape is showing the location for a net, rather than being the actual shape that should be used to generate the mask-patterns for manufacturing.
Select the metal1 shape at the top of the layout and look at its properties. Click the “Connectivity” button in the properties dialog box. You’ll notice that the Net Name is set to “VDD!”. This is showing that the extractor recognized the labels in the layout and assigned net names according to the labels. Check the other shapes in the design, and you’ll find that all of the label names that you used are preserved.
Perform an LVS Check
Now, in the layout window, select Verify->LVS… .
NOTE: If you are running LVS multiple times, you may see a dialog box warning you that the “LVS Run directory does not match the Run Form”. If you select the “Form Contents” option, then the LVS dialog will be updated with the name of the cell that you are currently editing. Otherwise, if you choose the “Run Directory” option, the dialog will be updated with the values from the last LVS run.
Set the LVS form with the options shown above. Then click the “Run” button. In the CIW, you will see the message “LVS job is now started...” After a while, you should see the following dialog box appear:
This does NOT mean that the LVS check was passed… only that the LVS check completed. To find out if LVS was successful, click the “Output” button in the LVS form. You should see the following info:
Like matching is enabled. Net swapping is enabled. Using terminal names as correspondence points. Compiling Diva LVS rules... Net-list summary for /afs/unity.ncsu.edu/users/w/wdavis/class/ece746/04/cadence/LVS/layout/netlist count 6 nets 5 terminals 2 pmos 2 nmos Net-list summary for /afs/unity.ncsu.edu/users/w/wdavis/class/ece746/04/cadence/LVS/schematic/netlist count 6 nets 5 terminals 2 pmos 2 nmos Terminal correspondence points N3 N4 A N4 N6 B N0 N2 Z N2 N1 gnd! N1 N0 vdd! The net-lists match. layout schematic instances un-matched 0 0 rewired 0 0 size errors 0 0 pruned 0 0 active 4 4 total 4 4 nets un-matched 0 0 merged 0 0 pruned 0 0 active 6 6 total 6 6 terminals un-matched 0 0 matched but different type 0 0 total 5 5
Perform an LVS Check with Errors
You should not assume that LVS was successful unless you see the message “The netlists match” in this output. Just as an example of what can go wrong when running LVS, try removing the piece of metal1 that connects the PMOS source node to VDD! in the upper right-hand corner of the layout, as shown below. Then save the design, extract it again, and re-run the LVS check. You should see the following output.
Like matching is enabled. Net swapping is enabled. Using terminal names as correspondence points. Compiling Diva LVS rules... Net-list summary for /afs/unity.ncsu.edu/users/w/wdavis/class/ece746/04/cadence/LVS/layout/netlist count 7 nets 5 terminals 2 pmos 2 nmos Net-list summary for /afs/unity.ncsu.edu/users/w/wdavis/class/ece746/04/cadence/LVS/schematic/netlist count 6 nets 5 terminals 2 pmos 2 nmos Terminal correspondence points N3 N4 A N5 N6 B N0 N2 Z N2 N1 gnd! N1 N0 vdd! Ill-defined correspondence points. N0 N2 Purged because neither is a subset of the other N3 N4 Purged because neither is a subset of the other N0 N2 Purged because neither is a subset of the other N5 N6 Purged because neither is a subset of the other N1 N0 Purged because neither is a subset of the other N1 N0 Purged because neither is a subset of the other Device summary for layout bad total pmos 2 2 Device summary for schematic bad total pmos 2 2 4 net-list ambiguities were resolved by random selection. The net-lists failed to match. layout schematic instances un-matched 2 2 rewired 0 0 size errors 0 0 pruned 0 0 active 4 4 total 4 4 nets un-matched 3 2 merged 0 0 pruned 0 0 active 7 6 total 7 6 terminals un-matched 2 2 matched but different type 0 0 total 5 5 Probe files from /afs/unity.ncsu.edu/users/w/wdavis/class/ece746/04/cadence/LVS/ schematic devbad.out: I /M3 ? Device does not cross-match. I /M4 ? Device does not cross-match. netbad.out: N /vdd! ? Net does not cross-match. It has 3 connections. N /Z ? Net does not cross-match. It has 3 connections. mergenet.out: termbad.out: T -1 Z /Z ? Terminal Z in the schematic failed to match any terminal in the layout. T -1 vdd! /vdd! ? Terminal vdd! in the schematic failed to match any terminal in the layout. prunenet.out: prunedev.out: audit.out: Probe files from /afs/unity.ncsu.edu/users/w/wdavis/class/ece746/04/cadence/LVS/ layout devbad.out: I /+3 ? Device does not cross-match. I /+2 ? Device does not cross-match. netbad.out: N /vdd! ? Net does not cross-match. It has 4 connections. N /Z ? Net does not cross-match. It has 4 connections. N /6 ? Net does not cross-match. It has 1 connections. mergenet.out: termbad.out: T -1 Z /Z ? Terminal Z in the layout failed to match any terminal in the schematic. T -1 vdd! /vdd! ? Terminal vdd! in the layout failed to match any terminal in the schematic. prunenet.out: prunedev.out: audit.out:
How would you figure out what the problem is from all this information? One thing that you should notice is that the number of nets is listed as 7 in the layout, but only 6 in the schematic. That means that there is an open circuit somewhere. You can select nets in the extracted view to make sure that everything is connected as you think it should be. In general, fixing LVS errors can be hard, so it’s a good idea to add hierarchy to your layout (explained in the next tutorial) and keep things from getting too complex.
Extract with Parasitic Capacitances
Next, fix the layout of the nand2 gate and save the design. Now we’re going to extract the wire capacitances from the layout.
Next, select Verify->Extract… . Set the options as before, but this time click the “Set Switches” button. In the dialog box that appears, select “Extract_parasitic_caps” and click Ok. You should see that string appear in the “Switch Names” field of the Extract form. Click Ok. Again, you should see the confirmation in the CIW that the extraction completed successfully. You should also see some lines indicating that wire capacitors were created, such as the following:
4 pcapacitor ivpcell NCSU_Analog_Parts parasitics created.
Create a SPICE Netlist with Parasitics
Next, open up the extracted view and select Tools->Analog Environment. Create an HSPICE netlist for this view, just as you would for a schematic. The result should look something like the following:
* # FILE NAME: /AFS/UNITY.NCSU.EDU/USERS/W/WDAVIS/CLASS/ECE746/04/CADENCE/ * NAND2/HSPICES/EXTRACTED/NETLIST/NAND2.C.RAW * NETLIST OUTPUT FOR HSPICES. * GENERATED ON SEP 13 21:13:33 2004 * FILE NAME: MYLIB_NAND2_EXTRACTED.S. * SUBCIRCUIT FOR CELL: NAND2. * GENERATED FOR: HSPICES. * GENERATED ON SEP 13 21:13:33 2004. C3 B VDD! 31.04E-18 M=1.0 C5 A VDD! 23.28E-18 M=1.0 C7 GND! B 31.04E-18 M=1.0 C9 GND! A 23.28E-18 M=1.0 C11 Z VDD! 35.1E-18 M=1.0 C13 B Z 156.18E-18 M=1.0 C15 GND! VDD! 17.36E-18 M=1.0 C17 GND! Z 31.9E-18 M=1.0 M19 VDD! B Z VDD! TSMC20P L=200E-9 W=600E-9 AD=299.999987959237E-15 +AS=180.000003617564E-15 PD=1.60000001869776E-6 PS=600.000021222513E-9 M=1 M21 Z A VDD! VDD! TSMC20P L=200E-9 W=600E-9 AD=180.000003617564E-15 +AS=299.999987959237E-15 PD=600.000021222513E-9 PS=1.60000001869776E-6 M=1 M23 Z B 1 GND! TSMC20N L=200E-9 W=600E-9 AD=299.999987959237E-15 +AS=90.0000018087821E-15 PD=1.60000001869776E-6 PS=300.000010611257E-9 M=1 M25 1 A GND! GND! TSMC20N L=200E-9 W=600E-9 AD=90.0000018087821E-15 +AS=299.999987959237E-15 PD=300.000010611257E-9 PS=1.60000001869776E-6 M=1 .lib "/ncsu/cadence/local/models/hspice/public/publicModel/tsmc20P" PMOS .lib "/ncsu/cadence/local/models/hspice/public/publicModel/tsmc20N" NMOS * INCLUDE FILES
Note that capacitors have been created for ever pair of overlapping nets. This is the most advanced form of parasitic extraction currently available with the NCSU CDK. A more advanced parasitic extraction tool would allow extraction of adjacent wires, as well as wire resistances. For now, you should assume that this is the most accurate representation of parasitics that we will use in this class for custom layout. For standard-cell layouts, we will use a 2.5D Extractor (in the Place & Route Tutorials).
Note also the AD and PD parameters for transistor M25 in the netlist above, which are 0.09 um^2 and 0.3 um, respectively. This is because the drain of this NMOS transistor is considered to be half of the active area between the two fingers of the NMOS p-cell, which is 0.15um by 0.6um. Note that this is following our method for hand-extraction of source & drain areas and perimeters! You may thus rely on extracted HSPICE netlists to have the most accurate source- and drain-capacitances in addition to wire capacitances.
Congratulations! You have completed the tutorial.
ECE 546Students: Save your final netlist (with capacitors) and submit using Wolfware. Also submit your LVS results (make sure that the netlists match for full credit).