Tutorial:CDK Layout Tutorial
In this tutorial you will go through creating an Inverter layout while performing design-rule checks (DRC). This tutorial assumes that you have logged in to an EOS machine and are familiar with basic UNIX commands.
Start the Cadence Design Framework
- Type “add cadence” at the command prompt. This will add the tool to your search path.
- Make directory called something like LayoutTutorial. Change to this directory.
- Start the Cadence Design Framework by typing “icfb &” at the command prompt.
% add cadence_cdkoa % add cadence2010 % mkdir LayoutTutorial % cd LayoutTutorial % virtuoso &
The first window that appears is called the CIW (Command Interpreter Window).
Another window that appears is the Library Manager. This window allows you to browse the available libraries and create your own.
Create Layout View of an Inverter
Create New Library
In the Library Manager, create new library called mylib. Select File->New->Library. This will open new dialog window, in which you need to enter the name of your library, library path, and "Attach to existing tech library" (TSMC 0.20u should be selected). You can leave the “Path” field blank, or set it to “.”. the library will be created in your working directory. After you fill this all out, the window should look something like this:
You should see the library “mylib” appear in the Library Manager.
Create New Layout View
Select the library you just created in the Library Manager and select File->New->Cell View… . We will create a layout view of an inverter cell. Simply type in "inv" under cell-name and "layout" under view. Click OK or hit "Enter". Note that the “Tool” is automatically set to “Virtuoso”, the layout editor.
Alternatively, you can select the "Virtuoso" tool, instead of typing out the view name. This will automatically set the view name to "layout".
After you hit "OK", the Virtuoso screen will appear as shown below. In addition, the LSW window (Layer Selection Window), which shows various mask layers, will automatically pop up.
Now you are ready to draw objects in the Virtuoso window. In this section you learn to place copies of other cells: pmos, nmos, ptap, and ntap. These cells are parameterized cells (or “p-cells”) which change their features when you change their parameters.
In Layout Editor select Create->Instance, or simply hit “i”. This will pull up the “Create Instance” dialog box. Next, click “Browse” on the screen that appears and select the library “NCSU_TechLib_tsmc02”, cell “nmos”, view “layout”. Click “close” on the browser window. Then scroll down in the create-instance dialog to look for a property called “Width”. Make sure this is set to 300n. Next, place the NMOS transistor so that your layout looks like the window below. Next, in the create-instance dialog box, change the cell from “nmos” to “pmos” and the width to 600n. Place the pmos roughly as shown below. Finally, hit “Escape” to stop adding instances.
Now, you will notice that you don't immediately see what is inside the nmos symbol. You can fix this by hitting Shift-F to display all levels of hierarchy. (You can also do this by going to the Virtuoso Options menu, choosing Display and setting Display Levels from 0 to 32) To switch back, hit CTRL-F, or set the Display Levels back to 0 from the Options menu.
Your nmos transistor probably looks very small on the screen. To zoom in, hit “z”, then left-click and draw a box around the area you want to zoom in. Alternatively, you can hit “f” to “fit” the entire design in the window, or SHIFT-Z and CTRL-Z to zoom in and out by factors of 2.
Use the commands above to show the layout as below.
Now, look now at the LSW (Layer selection window). This window shows you the names of the layers that are “valid” (meaning that you can manipulate them). You can figure out which layers are part of the NMOS cell by making them visible and in-visible. To toggle a layer’s visibility, middle-click on the name of the layer in the LSW. You can make all layers visible with the “AV” button, and no layers visible with the “NV” button. Hit CTRL-R to “redraw” the Virtuoso window after you’ve changed the visible layers.
Note that even if you make all layers invisible, you may still see some shapes. This is because not all layers are “valid”. Shapes in invalid layers cannot be altered and are always visible. To make all layers valid, you can choose Edit->Set Valid Layers… in the LSW. In general, it is recommended that you not set all layers as valid, because this clutters up the LSW with many unused layers.
Using this approach, you should be able to figure out that the NMOS uses the following layers: nactive, nselect, poly, metal1, cc. The PMOS is like it, exept that it uses layers pactive, pselect, and nwell instead of nactive and nselect. Note that the NMOS does not use the pwell layer. This is because this is assumed to be a p-substrate process. Note also that there is nothing magical about the p-cells. You could paint these shapes manually in the current cell-view, and it would make no difference whatsoever to the tool. However, it’s much less effort to use the p-cells, so that’s what we’ll do.
Selecting and Moving Layout
By default, if you simply drag out a region while holding down the left mouse button (Button-1), whatever is within the box will be selected and highlighted in white.
- Drag a box over the nmos you just instantiated. When you release the mouse button, whatever is "selected", in this case the nmos cell, will be highlighted.
Once you have selected an object (that is, an instance or a shape) you can do lots of things with it.
- For example you can move it by typing the m hot-key. You can move layout up/down/left/right one grid at a time by clicking at the selection and moving the mouse. Try it.
You can also select objects by clicking on them.
- Clicking the left mouse button once on an instance or shape selects it.
If you didn’t place your NMOS and PMOS cells exactly as illustrated above, try moving them now until they are.
To perform a Design Rule Check (DRC), choose Verify->DRC…. The DRC form appears:
Make sure that the “Echo Commands” box is unchecked, or DRC will take a lot longer to complete (because it will write lots of text to the CIW). For larger designs than this one, this text can be a nice “status indicator” to show how far the DRC check has progressed, but for now, it just makes things slower.
Click OK to run DRC. You should see some markers appear, as shown below.
Viewing DRC Errors
You can learn about the errors by selecting Verify->Markers->Explain and clicking on a marker. Alternatively, you can select Verify->Markers->Find… and click “Next” to cycle through all of the error. Errors are described in the marker text window like this one.
In this particular case, Source/Drain active was too close to the n-well edge. Fix this error by moving up the pmos. It’s good practice to space the NMOS and PMOS transistors by the smallest amount allowed in order to make the layout as dense as possible.
Move the PMOS and re-verify until there are no DRC errors. You will know that there are no errors when there are no markers and you see the following message in the CIW:
********* Summary of rule violations for cell "inv layout" ********* Total errors found: 0
To learn more about each design-rule, follow the links the the “Tool Tips” section of the course web-page, under “Design Rules”.
To figure out how far to move the PMOS, you can hit “k” to draw a ruler. You can delete all of the rulers that you have drawn by hitting SHIFT-K.
If you simply want to remove the error markers, choose Verify->Markers->Delete All…. Then hit OK in the dialog box to delete all error flags.
Once you are done, your layout should look like the one below:
We are now going to "paint" a piece of poly to connect the pmos and nmos devices together. We do this by creating a shape, in this case, a rectangle.
- Select the poly layer in the LSW by left-clicking on it.
- Hit “r” to draw a rectangle and draw the poly area.
- Hit “Escape” to stop drawing rectangles.
- Your layout should look like this:
Another type of shape that you can create is a paths. Connect the drain nodes of the NMOS and PMOS transistor as follows:
- Select the metal1 layer in the LSW by left-clicking on it.
- Hit “p” to create a path.
- Set the Width to 0.4 in the dialog box.
- Click on one end of the path, and double click to end the path.
- Hit “Escape” to stop drawing paths.
- Your layout should look like this:
If you don’t like the way your drawing turned out, you can select a shape and delete it with the delete key, or you can hit “s” (for stretch), and click on one of the sides of a path or rectangle to stretch it into the position that you like.
Also, you may want to run DRC checks periodically to make sure you're making progress in good direction. It’s also a good idea to save occasionally, by selecting Design->Save or hitting “F2”.
Next, create strips of metal1 for VDD and GND. We typically make these shapes as horizontal bars across the top and bottom, and therefore call them “supply rails”. We then need to connect the rails to the source nodes of the transistors. Create these rails now, and make your design look like the one below. Again, try to make the layout as compact as possible and the supply rails as thin as possible, running DRC as often as needed to learn the design rules.
Next, we need to add contacts to wells, which serve as the bulk node of the transistors. Transistors do not have well-contacts by default, because they take up so much room. Several transistors can often share the same well-contact. In this class, we will require that every gate (that is, NOT, AND, OR, XOR, etc.) has at least one contact to each well. We can make these contacts by creating instances of two new p-cells: ntap and ptap.
Create an instance of the ntap cell and place it as close as possible to the PMOS transistor. Likewise, create an instance of the ptap cell and place it as close as possible to the NMOS transistor. Again, try to make the layout as dense as possible. When you are done, your layout should look approximately like the one below.
To finish our layout, we will add a gate-connection in metal1, with a metal1-to-poly contact (also called a via). Do this by choosing Create->Contact... or simply hit "o". You should see the Create Contact pop-up appears, as shown below:
Make sure that the contact type is set to M1_POLY. The other options should be set correcly by default. Position the via as shown below.
Lastly, we need to create pins so that the nodes in our layout have names that are human-readable. Create these pins by selecting Create->Pin…. Set the “mode” to “shape pin”, and the dialog box should change to match the view below. Type the names vdd!, gnd!, in, and out in the “Terminal Names” text-box as shown below. Select “Display Pin Name”. Leave all other options as they are.
Next, click the “Display Pin Name Option…” button. You will see another dialog box appear:
Set the height to 0.2 um and the layer to “metal1-dg (drawing)”. Click OK.
Next, click on the layout where you want each pin to be placed. You will need to click three times: twice to create a rectangle for the pin, and a third time to place the label. The shape of your rectangle doesn’t really matter, as long as it only covers area that is already covered by metal1-dg. Make sure that you don’t put the label on top of a contact hole, because you won’t be able to see it (the contact hole has a higher “priority”, meaning that the black square will be drawn on top of your label, obscuring it). When you are done, your layout should look like the one below.
Congratulations! You have completed the tutorial. Save your design and select Design->Plot->Submit to print out a copy of your layout.
ECE 546Students: Hand-in this print-out of your layout. Make sure that your layout is as dense as possible. Points will be deducted for layout that is larger than necessary.
If you would like to learn more about the layout editor, you can work through chapters 1-4 of the “Cell Design Tutorial” that comes with the Cadence documentation. Start the documentation browser by typing “cdsdoc &” at the command prompt, and then selecting Layout Editor->Cell Design Tutorial in the browser window that appears. This should start an HTML browser that displays the table of contents for the tutorial. If you find that you cannot view the figures correctly in the web browser, you can click the View/Print PDF link at the top of the page to launch a PDF viewer for the tutorial. This documentation browser offers many more links for you to learn about the Cadence Design Framework.