Tutorial:ASIC Design Tutorials

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INTRODUCTION

The tutorials in this section are used in ECE 520 ASIC Design. This course deals with the design of complex digital systems, their synthesis and their verification. To this end, students are given an introduction to the necessary CAD tools, particularly for simulation and synthesis of such systems. The following tutorials progressively build up the knowledge base required.


Tutorial1: Introduction to Simulation and Synthesis

The tutorial can be downloaded at: pdf doc (last modified Sep 06, 2016 [Synthesis files last modified Feb 08, 2015])

This tutorial provides a brief introduction to the tools that are going to be used for design of ASIC systems. To this end, we will be using Mentor Graphics Modelsim for simulation and the Synopsys Design Compiler environment for synthesis. It is interesting to note that the Modelsim tool enables compilation of multiple design/verification/modeling units (each of which might be in a different language) into a common library (called the working library) and a common design representation. This enables each individual unit of the entire simulation to be compiled independently and incremental compilation to be performed.

This tutorial was developed using a Red Hat Enterprise Linux workstation running RHEL 5.11.

The files that are needed for this tutorial are listed below. (please download and store per the instructions provided within the tutorials):


Tutorial2: Introduction to Methodology for Design Analysis

The tutorial can be downloaded at: pdf doc (last modified Sep 16, 2015)

This tutorial provides an example-based step-by-step introduction to the methodology that is going to be followed for the analysis of designs. The aim is to provide a realistic power and timing value for a design by running the design through a prototyping flow that provides a layout-based view of the circuit performance. This requires that you start off with the netlist that results from synthesis as explained in Tutorial 1. This Tutorial also provides information on the directory structure that is going to be followed for organization of your work. The main logical steps of this tutorial are (starting with a synthesized netlist per Tutorial 1):

  • The PAD_Flow.pl script that comes with this tutorial is run to create the Standard Parasitic Exchange Format (SPEF) file. This file captures the capacitance and resistance of the wiring network in your design. This is explained in Section 5.a of the tutorial.
  • The testbench is modified to be able to capture the toggling statistics of the nets in the design. This information is captured in a Switching Activity Interchange Format (SAIF) file. The method for doing this is explained in Section 5.b. THIS IS A MANUAL STEP.
  • The PAD_Flow.pl script is run to create final power and delay information for the design using the SAIF and SPEF files from the previous steps. This is explained in Section 5.c of the tutorial.

The files that are needed for this tutorial are listed below. (please download and store per the instructions provided within the tutorial):

  • PAD_Flow.pl The automation script for analysis.
  • synth.tcl A tcl script for running automatic synthesis.
  • auto.tcl A tcl script for doing automatic power estimation.
  • counter.v The design that we are working with. It is a larger version of the counter from Tutorial 1.
  • test.v The initial testbench for the Design Under Test.
  • test_switching.v The testbench with commands for SAIF creation that will be used in Section 5.b.
  • modelsim.ini Copy to ./SIMULATION/run_f and ./SIMULATION/run_s after setup
  • Library_fwd.saif Copy to ./SIMULATION/run_f after setup
  • designenv.tcl Copy to ./SYNTH/run_f after setup

Tutorial 2 Extension (added Sep 12, 2017)


Tutorial3: Complex Design Example and Memory Generator

The tutorial can be downloaded at: pdf doc (last modified Feb 08, 2015)

This tutorial provides the reasoning and steps to be followed in designing more complex systems. Dealing with IO requirements, hierarchy, and separation of control and data paths is explained. The creation of SRAMs using Memory Generators is explained and the incorporation of Memory Models in the timing and power analysis of a design is shown.

This tutorial was developed using a Red Hat Enterprise Linux workstation running RHEL 5.11.

The files that are needed for this tutorial are listed below (please download and store per the instructions provided within the tutorial):

  • CreateModel.pl The Memory Generator script. (UPDATED: April 4)
  • Engine.v The search engine that forms the core of the datapath.
  • Controller.v The Controller that manages the operation of the datapath.
  • top_with_mem.v The file that integrates top.v and the Memory Model.
  • top.v The top level integration of the controller and the engines.
  • test.v The initial testbench for the Design Under Test.
  • test_switching.v The testbench with commands for SAIF creation.
  • cache.cfg Cache configuration.
  • memdata.txt The 8 bit memory image that will be loaded into the memory array using $readmemh().

UPDATED: April 11: The following document explains the means of performing the power analysis with multiple memories can be downloaded from TwoMemories.pdf. The document uses two memories to illustrate the method but this can easily be extended to multiple memories. The necessary files for this document are:

  • top_with_2mem.v The file that integrates top.v and two memories instead of just one.


Tutorial4: FPGA Design Flow using Xilinx ISE Environment

The tutorial can be downloaded at: pdf doc

This tutorial provides a brief overview of how to design hardware systems for FPGAs. It assumes knowledge of Verilog, and will show you how to take an existing Verilog design, and target it to a specific FPGA. This is a useful skill in industry because many designs are prototyped using FPGAs due to quick time-to-market and low initial cost. This tutorial will cover how to access the Xilinx software at NC State, then will cover Design Input, Synthesis, Constraining, Implementation and Bitstream Creation.

The files that are needed for this tutorial are listed below. (please download and store per the instructions provided within the tutorial):


Tutorial5: DesignWare Instantiation

The tutorial can be downloaded at: pdf doc (last modified Feb 08, 2015)

DesignWare provides high quality IP to reduce risk and time-to-market which makes it very useful in ASIC design. This tutorial provides an example of instantiation of a floating point adder/subtractor using DesignWare IP.

This tutorial was developed using a Red Hat Enterprise Linux workstation running RHEL 6.6 using synopsys2013 and modelsim10.0c

The files that are needed for this tutorial are listed below. (please download and store per the instructions provided within the tutorial):


Tutorial6: FPGA Design Using Altera

The tutorial can be downloaded at: pdf doc (last modified Jun 05, 2015)

This tutorial provides a brief overview of how to design hardware systems for FPGAs. It assumes knowledge of Verilog, and will show you how to take an existing Verilog design, and target it to a specific FPGA. This is a useful skill in industry because many designs are prototyped using FPGAs due to quick time-to-market and low initial cost. This tutorial will cover how to access and use the free Web version of Altera's simulation and design tools.


Tutorial7: Downloading and Using the Student Version of Modelsim

Here's how to download the student version of Modelsim SE, so you can use it locally if remote access is unavailable.

  1. Download the student version of Modelsim SE from model.com.
  2. Install it on your local machine.
  3. Follow the instructions on the website and provide your email address. A license will be sent to you via email.
  4. Copy the necessary modelsim.ini file from a tutorial webpage and save it in the following directory:
    "installation directory"/examples
    This is the default directory when you run modelsim. If you change the running directory, please remember to save "modelsim.ini" there.
  5. Copy all your design files and testbench file into the same directory:
    "installation directory"/examples
    Again, you can change your working directory if needed.
  6. Launch modelsim, and use the same commands that we do on Linux machines
    setenv MODELSIM modelsim.ini
    vlib mti_lib
    Compile your design and testbench using "vlog"
  7. Double-click the top level test bench module in subwindow "library->mti_lib"
  8. You should be able to run a simulation of any duration now.