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This tutorial introduces the Pathfinder3D tool for architecture evaluation. In this tutorial you will analyze a simple simple and complex designs to illustrate the features of Pathfinder3D.

Creating an Account

Before you can use Pathfinder3D, you'll need to request account. Click the link in the upper right that reads Register a New Account or Forgot Password? and follow the instructions. You will be sent an e-mail to activate your account. After you log in, you can change your password in your account settings.

Evaluating a Simple System

Once you have logged in to Pathfinder3D and changed your password, click the Upload link in the upper-right. This will take you to a page where you can upload command files for analysis. Here we will go through a simple set of command files and then discuss the analysis results.

Uploading Files

Technology File

First, set a technology description. Click the Edit Manually button to the right of the Technology box and copy the following text into the box.

    materials: [
      # Name       thermalK(W/(m-K))
      [ Si         100  ]
      [ SiO2       1    ]

    waferTechnologies: [
      { name:example1
        layers: [
        # [ name   thickness material  [ db_layer material ] ... ] 
          [ substrate  40e-6 Si   ]
          [ active    200e-9 Si   ] 
          [ metal      10e-6 SiO2 ]

    stackTechnology: {
      tiers: [
        # tier  name    wafer_tech       facing  start               stop       boundary
        #                                        layer               layer      layer
        # ----  ------   ---------------  -----  -------------------- ---------  -----------
        [ layer handle 1e-3 Si ]
        [ tier  A        example1         up     active               metal                  ]
      vias: [

      # name        start                 stop          tier db_layer  show 
      [ handle      [layer handle]                                           ]
      [ activeA     [tier A active]       None            A  active_A  True  ]
      [ metalA      [tier A metal]                                           ]
Command File Syntax

The first thing to notice about this file is its syntax. All commands to Pathfinder3D are in the form of strings, numbers, lists (indicated by square-brackets [ ]), and sets of name-value pairs called dictionaries (indicated by curly-braces { }). The pound-sign # indicates that the remainder of the line is a comment. For those familiar with Python, this is an abbreviated form of the Python grammar with the quotation marks and commas removed for brevity. Each command file must contain one top-level dictionary. If this dictionary has mismatched brackets or braces, then the server will issue a parse error.

Technology Commands

The Technology file above contains one top-level dictionary with one key called technology. The value for this key is another dictionary with 4 keys, detailed below:

  • materials - This section gives a list of material names and thermal conductivities for static thermal analysis. This section will be expanded in future versions to include heat capacity and density for dynamic thermal analysis.
  • waferTechnology - This section gives a list of single-wafer manufacturing technologies and its associated layer list for each. Currently, only one wafer technology is listed, named example1, however you may define as many as you like. The layer-list defines a name for each layer, a thickness and a "background" material. The "foreground" materials are omitted in this example but will be covered in the next example. This technology is simplified and has only 3 layers: a 40um thick substrate, a 200nm active layer, and a 10um thick metal area. Normally, as we will see in the next example, you would include all layers in a technology, but this simple example helps to better illustrate the tool for now.
  • stackTechnology - This section gives a single stacking technology for the 3D-IC system. the tiers section gives a list of named tiers, each one an instance of the wafer-technologies listed earlier. A facing is given (up or down) and a start and stop layer. The boundary layer capability is currently unsupported and can be ignored. In addition to tiers, a set of "glue layers" can also be specified. These are layers that are used during the stacking process and are not necessarily a part of the wafer technology. In this case, we assume that the substrate of the first tier is a "glue-layer". This layer is sometimes called the "handle" when it provides the primary structure for holding the circuit together. Because this layer is often thinned to different degrees during the stacking process, we consider it to be a "glue-layer", rather than part of the tier. Vias are also listed here, but these will be discussed more in the next example.
  • compositeModel - The wafer technology given here has only three layers, but a real technology will typically have more than 20. Analyzing a stack in that much detail takes a lot of time and may not be necessary. This section provides a reduced list of "composite layers" to model the complete stack, including the start and stop layers from the stackTechnology section. Because our wafer technology only contains 3 layers, this file doesn't reduce our model yet, but it will once our technologies get more complex. For now, note the three remaining arguments for the activeA composite layer:
    • tier - This string indicates that power injected in this tier will appear in this composite layer. Currently, Pathfinder3D models only transistor channel heating. Future versions may support heating within the metal-oxide composite (often called "Joule heating") but this is not currently planned. This string will be used later in the Design file to indicate where heat will be inserted.
    • db_layer - This string indicates which OpenAccess database layer will be used to indicate a heat source. Currently, Pathfinder3D assumes the use of the FreePDK3D45 database, and so this layer must be a valid layer from that design kit. It must also be distinct from the layer specified for other tiers. This information is needed to facilitate the linkage to the WireX tool for thermal model extraction.
    • show - This argument specifies whether or not to show analysis results for this composite layer.
Boundary Conditions

One final note on the technology file. For thermal analysis, it is necessary to specify a set of boundary conditions. The WireX tool currently supports only one style of boundary condition, which is a perfect heat sink on one face of the stack and adiabatic (no heat flow) on all other faces. The perfect heat sink is assumed to be connected to the first layer or tier specified in the stackTechnology. All temperatures will be reported as a rise above this heat sink. For absolute temperatures, the temperature at this interface must be determined through simulation of the package and physical heat-sink using the same total power assumed here. This model is accurate, as long as the handle substrate is a perfect heat-spreader, which is not always an accurate assumption. For this reason, users may want to model portions of the package and heat-sink as "composite layers" in the Pathfinder3D technology file, but that is out of the scope of this tutorial!

Interfaces File

The interfaces file defines a set of interfaces to be used in the design file. This file is used to expand transaction-level model (TLM) sockets into register-transfer-level (RTL) ports for repeater power, delay, and routability estimates. This capability is not yet implemented but is planned for release by early 2012. In the meantime, this section can safely be left blank.

Design File

Next, set the design description. Click the Edit Manually button to the right of the Design box and copy the following text into the box.

      { name:mycell tier:A height:1000 width:1000 }

      { name:i0 master:mycell loc:[0 0]}

The design dictionary defines a set of macrocells, each with a name, tier, and dimensions in microns. In this case, one macrocell is defined in tier A. The tier name must correspond to one of the tier names defined in the compositeModel section of the technology dictionary. The dimensions of this macrocell are set at 1mm by 1mm.

Next come the instances. A name must be given, along with the name of a master that is defined in the macrocells section. A location must also be given, which are x and y positions in microns.

Stimulus File

Finally, set the stimulus description. Click the Edit Manually button to the right of the Stimulus box and copy the following text into the box.

      [i0 1.0]

These power section of the stimulus dictionary allows specification of a specific total-power value for each instance in Watts. In the future, this section will allow different methods of specifying power to allow time- and temperature-dependent analyses. For now, however, a simple value of 1W is given for the one instance in the design.

Note that if you want to skip the thermal analysis, you may leave this section blank. However, the server currently requires that you at least supply an empty dictionary (i.e. the string "{}") for this file.

Analyzing the System

Once the input values are set, click the Evaluate System button at the bottom of the Upload page. You should see the message "Your data has been submitted!" appear at the top of the page.

Next, click on the "My Account & Results" link at the upper right of the page. You will see a section labeled "My Paths," which contains the results of all the analyses you have requested. If the Pathfinder3D server is still processing your request, you will see that the status is "Queued". Once complete, you should see the status is updated to "Success" and link is provided to view the results. If the analysis failed, then a link is provided to view the error message and stack trace. In this event, please e-mail us at for help.

Assuming that there were no errors, click now on the analysis results for this run. You will see a page with a floorplan for tier A that is 1000 um by 1000 um. This floorplan is not very interesting to look at, because it contains only one block. You will also see a legend with temperatures ranging from 10.0006 Kelvin to 10.0011 Kelvin. Finally, there is a 10x10 grid of analysis points overlaid on the floorplan.

This simple design serves as a sanity check to make sure that the thermal analysis is working as we would expect. The thermal system as we have set it up is essentially 1W flowing through a 1mm x 1mm x 1mm cube of silicon (the handle substrate), which has a conductivity of 100 W/(m-K). The temperature gradient should therefore be (1W)*(1mm)/(1mm)2/(100W/(m-K))=10 Kelvin, which is what our analysis is showing down to nearly 3 decimal places. The difference comes from the fact that the active layer has a finite thickness and also finite word-length errors.

Recall that this is a temperature rise above the handle. If you wanted to know what the actual temperature is, then you would need to add this value to the temperature of the surface of the handle. One way to estimate that temperature would be to assume a package and heat-sink thermal resistance (1 K/W is often assumed), multiply it by the total power of the system, (1W in this case) and add it to the ambient temperature (25 degrees C, for example). In this example, that would a temperature on tier A of 25+(1)*(1)+10 = 36 degrees C.

Evaluating a More Complex System

Now that we have some idea that the tool is working properly, let's analyze a more interesting system. Click on the "Upload" link again to return to the file upload page. Note that you can click the link "Load Data from Last Attempt" in the "Tools" bar if you want to edit the same files that you uploaded before and tweak them. In this case, we will load a new design, which is provided as default input for the tool. Click the button "Load Example Data" in the "Tools" bar to load this example.

Technology File

Examine the technology data. You'll notice that the waferTechnology contains the complete list of layers from the FreePDK45 metal layers page and that the stackTechnology contains a 5-tier technology with the facings, vias, and glue layers from the FreePDK3D45 metal layers page. Each layer definition now includes one or two "db_layers" and "materials" pairs that were not there before. These pairs specify database layers that indicate a material that takes the place of the default material for the layer. For example, the POLY layer lists the insulator SiO2 as its material, unless a shape is found in the "contact" database layer, in which case the CONT material is assumed. If a shape is found in the "poly" database layer, then the PolySi material is assumed, taking priority over both the CONT and SiO2 materials. This information is intended to be used when building a detailed model of layout for thermal analysis. Currently, however, this detailed layout data is not extracted, and so these database layer names can be anything you wish (but they must match the dbLayerDensities described below). It's a good idea, though, to have them correspond to actual database layers in a process design kit, so that users of this technology can have an idea of how changes in layout are likely to affect thermal properties.

Next, notice the new section that has been added to this file, titled dbLayerDensities. Because detailed layout information is not available, a structure must be assumed for each composite material in order to estimate its thermal conductivity. Here a density value is given (as a range from 0 to 1) coupled with a routing direction (horizontal, vertical, or cut). Using this information, a unit cell is constructed for each layer of the composite model, and an equivalent conductivity is estimated. For more information, please read the page that discusses how Pathfinder3D Calculates Thermal Conductivity.

Finally, note the new composite model. Three layers are used for each tier. The substrate and metal layers are split, because the conductivities differ by a factor of about 50. It helps the analysis to have the heat-spreading layers distinct from the less conductive layers. The third layer, active, needs to be distinct so that there is a finite volume in which heat can be injected.

Interfaces, Design, and Stimulus Files

We can still ignore the interfaces, since they're not used at the moment. Look at the design file. Note that two macros are defined on each tier, named "big[A-E]" and "small[A-E]" Height and width are specified for each one, and they are the same in all tiers. The key thing to note here is that macrocells cannot be moved between tiers. This may complicate the floorplanning process, but it greatly simplifies the back-end integration of heterogeneous technologies. Lastly, note that the "smallA" block has an area and aspect-ratio defined, instead of height and width. You may any two of the values height, width, area, and ar to specify your macrocell.

The instances section of the design file defines the floorplan. You'll see that each tier has 4 instances, labeled n, s, e, and w for north, south, east, and west. A location is given for each instance, along with a rotation value. Legal values for the rotation include all OpenAccess orientations: R0, R90, R180, R270, MY, MYR90, MX, and MXR90. These instances define a floorplan for a 9mm by 9mm chip in 5 tiers.

IMPORTANT NOTE: Currently, overlapping rectangles in the floorplan are not allowed. If you put overlapping rectangles in your floorplan, thermal analysis will be skipped. We hope to have this fixed by early 2012.

Finally, consider the stimulus file. You'll see that the random power values have been set for each instance. The total power adds up to 81 W. Note that for a 9mm x 9mm area, this corresponds to a power density of 100 W/cm2, which is typical for a high-performance microprocessor.

Analyzing the System

Click the Evaluate System button to analyze your design and check the results. You should see that the temperature rises range from a minimum of about 5.5 K (on the active layer of tier A, closest to the heat-sink) to a maximum of about 29.5 K (on the active layer of tier E, furthest from the heat-sink).

To help interpret these temperatures, scroll down to look at the details of the composite model. You'll see that upper and lower bounds on thermal conductivity have been calculated in the x, y, and z directions, and that a specific value had been chosen to be used for the thermal analysis (labeled "used" at the top of the column). These bounds are mostly important for the metal composite layers (labeled metal[A-E]), because these are the layers that represent a heterogeneous composite of metal and insulator. For details on how these bounds were calculated and why the specific values were used, please refer to the Thermal Conductivity Calculation page.

This completes the tutorial! From here, you can begin trying out your own technology files and designs. If you get errors that you can't explain, please contact us at