Layout

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I'm used to Magic. What are all these layers in the layout window?

We've made a brief description of the mask layers used. Also, using pcells can reduce the need to be intimately familiar with your technology.

What's the difference between nactive, pactive, cactive, tactive and plain old active?

nactive, pactive, cactive, and active are translated to the same CIF/GDSII layer. nactive, pactive and active can be used interchangeably, but it's easier to distinguish NFETs from PFETs on-screen if you draw them using nactive and pactive respectively.

cactive is used only to draw the collector region of NPN transistors in processes that support this option.

Note since all four are exported as active, if you import a CIF/GDSII file all four layers will also be imported as active. If you then want to convert them back, you can use the approriate extraction switch.

tactive denotes thick-oxide (i.e., high-voltage) devices, in processes that support this option, and is a different mask layer than the others.

How do I highlight an entire node?

Just click on it in the extracted view. (Clicking on a shape in the layout view will select just that shape, since the layout view doesn't contain connectivity information.) To deselect, click on an empty area. (If you find that this is interfering with any probing, you can set the variable NCSU_DontUseProbeHighlighting = t to use the old highlighting method.)

What's a good way to draw interconnect wires?

Use the path tool (select the "Create->Path..." menu entry). There's a facility to allow automatic placement of vias (path stitching), such as for going between metal 1 and metal 2.


Are any other layout macros available?

Each of the technology libraries (e.g. NCSU_TechLib_tsmc03) contains several "parameterized cells" (pcells). Pcells include MOS devices, all types of contacts and vias, and a thin-ox capacitor (where applicable). If you're going to do any layout, you should definitely read a little more about them.


How do I label a node?

Hit l or use the "Create->Label..." menu entry. Note that the label associates with the physically highest shape underneath the hotspot. E.g., if you create a label on an overlap of metal 1, metal 2, and poly, the label will associate with the metal 2. The CDK label-creation routine understands bus notation similar to that in Composer; e.g., use bus to label an 8-bit bus, or bus to label every other bit. Generally, these labels should be on the "text" drawing layer.

Another method, especially useful if the shape you want to label is underneath other layers and inaccessible, is to select the "Create->Pin..." menu entry. Use symbolic pins (which are located in the sym_pins category in either your design library or it's attached technology library) to label shapes that are obscured by shapes on other layers. Symbolic pins are not written out when you make a CIF or GDSII file.


I extracted my circuit from layout. If I hit "q" to get the properties on a transistor, the AD/AS/PD/PS values aren't correct. Why not?

The values you see in the properties dialog come from a simple heuristic: the source/drain rectangles are 2.5 times "minLength" on the top and bottom and "width" on the left and right. These are mainly useful for doing simulations from schematics. When you netlist your extracted view you should see the correct (i.e., measured) values.


How do I put a picture or text label on my chip?

Use the GIMP p2m plug-in.


How do I package my part?

The CDK includes MOSIS wirebond pads for some technologies. Check the appropriate CDK technology library for a wirebondPads category.


How do I make a mask file?

See the document on creating CIF or GDSII mask data with the CDK.