FreePDK45:RuleDevel

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This page is intended for proposing and discussing new design rules. The rules are listed in the order that decisions were made, along with a brief rule description and one or more notes giving a rationale. When possible, key-words in the rule description are linked to a set of standard Verification Rule Types.

Rule Value Description Notes
WELL.1 none saveDerived: nwell/pwell must not overlap (10)
WELL.2 225 nm Minimum spacing of nwell/pwell at different potential (10) (11)
WELL.3 135 nm Minimum spacing of nwell/pwell at the same potential (10) (11)
WELL.4 200 nm Minimum width of nwell/pwell (10) (11)
VT.1 none Vt adjust layers must coincide with well
POLY.1 50 nm Minimum width of poly (1)
POLY.2 140 nm Minimum spacing of poly AND active (2)
POLY.3 55 nm Minimum poly extension beyond active (3)
POLY.4 70 nm Minimum enclosure of active around gate (10) (11)
POLY.5 50 nm Minimum spacing of field poly to active (10) (11)
POLY.6 75 nm Minimum Minimum spacing of field poly (14)
ACTIVE.1 90 nm Minimum width of active (4)
ACTIVE.2 80 nm Minimum spacing of active (4)
ACTIVE.3 55 nm Minimum enclosure/spacing of nwell/pwell to active (5)
ACTIVE.4 none saveDerived: active must be inside nwell or pwell (8)
IMPLANT.1 70 nm Minimum spacing of nimplant/ pimplant to channel (10) (11)
IMPLANT.2 25 nm Minimum spacing of nimplant/ pimplant to contact (10) (11)
IMPLANT.3/4 45 nm Minimum width/ spacing of nimplant/ pimplant (10) (11)
IMPLANT.5 none Nimplant and pimplant must not overlap
CONTACT.1 65 nm Minimum width of contact (6)
CONTACT.2 75 nm Minimum spacing of contact (6)
CONTACT.3 none saveDerived: contact must be inside active or poly or metal1 (8)
CONTACT.4 5 nm Minimum enclosure of active around contact (8) (12)
CONTACT.5 5 nm Minimum enclosure of poly around contact (8) (12)
CONTACT.6 35 nm Minimum spacing of contact and poly (10) (12)
METAL1.1 65 nm Minimum width of metal1 (7)
METAL1.2 65 nm Minimum spacing of metal1 (7)
METAL1.3 35 nm Minimum enclosure around contact on two opposite sides (13)
METAL1.4 35 nm Minimum enclosure around via1 on two opposite sides (13)
METAL1.5 90 nm Minimum spacing of metal wider than 90 nm and longer than 900 nm (16)
METAL1.6 270 nm Minimum spacing of metal wider than 270 nm and longer than 300 nm (16)
METALl1.7 500 nm Minimum spacing of metal wider than 500 nm and longer than 1.8um (16)
METALl1.8 900 nm Minimum spacing of metal wider than 900 nm and longer than 2.7 um (16)
METAL1.9 1500 nm Minimum spacing of metal wider than 1500 nm and longer than 4.0 um (16)
VIA1.1 65 nm Minimum width of via1 (8) (9) 15
VIA1.2 75 nm Minimum spacing of via1 (8) 15
VIA1.3 none saveDerived: via1 must be inside metal1 (8)
VIA1.4 none saveDerived: via1 must be inside metal2 (8)
METALINT.1 70 nm Minimum width of intermediate metal (7)
METALINT.2 70 nm Minimum spacing of intermediate metal (7)
METALINT.3 35 nm Minimum enclosure around via1 on two opposite sides (13)
METALINT.4 35 nm Minimum enclosure around via[2-3] on two opposite sides (13)
METALINT.5 90 nm Minimum spacing of metal wider than 90 nm and longer than 900 nm (16)
METALINT.6 270 nm Minimum spacing of metal wider than 270 nm and longer than 300 nm (16)
METALINT.7 500 nm Minimum spacing of metal wider than 500 nm and longer than 1.8um (16)
METALINT.8 900 nm Minimum spacing of metal wider than 900 nm and longer than 2.7 um (16)
METALINT.9 1500 nm Minimum spacing of metal wider than 1500 nm and longer than 4.0 um (16)
VIA[2-3].1 70 nm Minimum width of via2 (15)
VIA[2-3].2 85 nm Minimum spacing of via2 (15)
VIA[2-3].3 none saveDerived: via2 must be inside metal2 (8)
VIA[2-3].4 none saveDerived: via2 must be inside metal3 (8)
METALSMG.1 140 nm Minimum width of semi-global metal (7)
METALSMG.2 140 nm Minimum spacing of semi-global metal (7)
METALSMG.3 0 nm Minimum enclosure around via[3-6] on two opposite sides (13)
METALSMG.6 270 nm Minimum spacing of metal wider than 270 nm and longer than 300 nm (16)
METALSMG.7 500 nm Minimum spacing of metal wider than 500 nm and longer than 1.8um (16)
METALSMG.8 900 nm Minimum spacing of metal wider than 900 nm and longer than 2.7 um (16)
VIA[4-6].1 140 nm Minimum width of via4 (15)
VIA[4-6].2 160nm Minimum spacing of via4 (15)
VIA[4-6].3 none saveDerived: via4 must be inside metal4 (8)
VIA[4-6].4 none saveDerived: via4 must be inside metal5 (8)
METALTNG.1 400 nm Minimum width of thin global metal (7)
METALTNG.2 400 nm Minimum spacing of thin global metal (7)
METALTNG.3 0 nm Minimum enclosure around via[6-8] on two opposite sides (13)
METALTNG.7 500 nm Minimum spacing of metal wider than 500 nm and longer than 1.8um (16)
METALTNG.8 900 nm Minimum spacing of metal wider than 900 nm and longer than 2.7 um (16)
METALTNG.9 1500 nm Minimum spacing of metal wider than 1500 nm and longer than 4.0 um (16)
VIA[7-8].1 400 nm Minimum width of via[7-8] (15)
VIA[7-8].2 440 nm Minimum spacing of via[7-8] (15)
VIA[7-8].3 none saveDerived: via[7-8] must be inside metal[7-8] (8)
VIA[7-8].4 none saveDerived: via[7-8] must be inside metal[8-9] (8)
METALG.1 800 nm Minimum width of global metal (7)
METALG.2 800 nm Minimum spacing of global metal (7)
METALG.3 0 nm Minimum enclosure around via[8-9] on two opposite sides (13)
METALG.8 900 nm Minimum spacing of metal wider than 900 nm and longer than 2.7 um (16)
METALG.9 1500 nm Minimum spacing of metal wider than 1500 nm and longer than 4.0 um (16)
VIA[9].1 800 Minimum width of via9 (15)
VIA[9].2 880 Minimum spacing of via9 (15)
VIA[9].3 none saveDerived: via9 must be inside metal9 (8)
VIA[9].4 none saveDerived: via9 must be inside metal10 (8)
GRID.[1-26] 2.5 nm Shapes on all layers must be on a 2.5 nm grid
ANTENNA.1 300:1 Ratio of Maximum Allowed (Field poly area or Metal Layer Area) to transistor gate area (17)

This table contains proposed rules to be completed and deemed necessary before being added to the rules file.

Proposed Rule Value Description Notes

Notes

(1) 50nm was chosen for the minimum width rectangle for poly, becasuse it is easier to design with than 45nm. It is assumed that the actual gate length is 45nm. In addition, the electron-micrograph in Fig. 18 in [3] appears to be about 50nm.
(2) Poly gate spacing is listed as 140 nm in Table 1 of [3]. Examining the electron-micrographs in other papers, the spacing appears to be 75nm in [2] and 125nm in [1]. In order to be a conservative set of rules, we should probably set the rule to be the largest of the three (namely, 140nm).
(3) Minimum poly extension beyond active varies from paper to paper, but appears to be on the order of the width of the poly line in most cases. Increased to 55 nm for manuracturablitiy based on advice from  ?????
(4) Table 1 in [1] and Table 1 in [3] both list minimum active width of 60 nm and spacing of 80 nm. However, Anupama Subramaniam of Marvell suggests that active width should be at least twice the gate length for better yield (giving 90nm).
(5) Min. spacing of N+ and P+ is listed as 102 nm in Table 1 of [2]. By setting the well/active enclosure/spacing to 55 nm, we effectively make this space 110 nm, which is slightly conservative and aligned to our 5 nm manufacturing grid.
(6) Contact width/space is given as 66/74 in Table 1 of [1] and 60/80 in Table 1 of [3] (giving a pitch of 140 nm in both cases). We chose 65/75 because it is in the middle and aligned to the 5nm grid, while still offering a pitch of 140 nm.
(7) Metal rules taken from the half/pitch values in table 1 of [2], which are nearly identical to the values in table 1 of [1] and table 4 of [3]. The only differences are that the width/space of metal1 are listed as 60/70 in [3] (still a pitch of 130 nm), and the global wiring has a pitch of 2000 nm in [1].
(8) Rules are taken from an example Diva DRC file in the Diva reference.
(9) Value taken from FreePDK45.tf, in which values were scaled down from an older technology.
(10) Rule taken from the NCSU CDK.
(11) Value taken from original MOSIS lambda-based rules.
(12) Extension of active area beyond gate appears to be about 100nm in Fig. 10 of [1]. Given the contact size of 65nm, and as small an active enclosure as possible (i.e. 5nm), a 35nm space of contact to gate is implied.
(13) Minimum via overlap value is taken from the 3-sigma overlay value in the 2005 ITRS for the 2007 technology node. This overlap is typically 2 times the overlay value. We have used 3 times this value and inflated it stightly to be conservative and to align to our manufacturing grid. Higher level metals do not have this requirement, so it is only applied to metal1 and the intermediate metal layers.
(14) Anupama Subramaniam from Kevin Cao's group suggested that field poly spacing should be 1.5 * poly half-pitch for improved yield.
(15) Width/spacing modified to reflect minimum lower metal width, and to be similar to contact rules.
(16) Variable width rules modeled off of GPDK version.
(17) [4] cites that antenna ratios for 180nm technology generally limited to 1000:1. This is total antenna surface ratio and is defined in Fig. 7 in [4]. C. Gabriel thinks 1000:1 ratio maybe unsuitable for 45 nm technology. Blaze DFM site claims the ratio will drop, but not clear from the evidence if this is true or not. [5] claims that oxide charging plasma current is in the range of 100nA to 1uA and states that it is unlikely to increase much for tox below 1.5nm (i.e. Lg below 65nm). This is supported in [6] which concludes saying impact of plasma damage is negligible for ultra-thin gate oxide below about 1.5nm. A metal:antenna ratio 300:1 is chosen, where 300 times antenna area is the maximum allowed cumulative metal area from metal 1 to last metal layer, to be conservative.

References

[1] H. Nii et. al, "A 45nm High Performance Bulk Logic Platform Technology (CMOS6)using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL," IEEE International Electron Devices Meeting (IEDM) Technical Digest, Dec. 11-13 2006.
[2] S. Narasimha et. al., "High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography," IEEE International Electron Devices Meeting (IEDM) Technical Digest, Dec. 11-13 2006.
[3] E. Josse et. al., "A Cost-Effective Low Power Platform for the 45-nm Technology Node," IEEE International Electron Devices Meeting (IEDM) Technical Digest, Dec. 11-13 2006.
[4] C. T. Gabriel and E. de Muizon, “Quantifying a simple antenna design rule,” 5th International Symposium on Plasma Process-Induced Damage, May 22-24 2000.
[5] D. S. Bang et. al, "Effect of Cu damascene metallization on gate SiO2 plasma damage," 3rd International Symposium on Plasma Process-Induced Damage, Jun. 4-5 1998.
[6] W. T. Weng et. al, "A Comprehensive Model for Plasma Damage Enhanced Transistor Reliability Degradation," 45th Annual International Reliability Physics Symposium, 2007.