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The following is pasted from the $PDK_DIR/ncsu_basekit/doc/FreePDK3D45_Manual.txt file, included in the distribution:

 Contents: Manual for the 3D version of the FreePDK45
 File: FreePDK3D45_Manual.txt
 Created: June 4, 2009

 Update History:
    Date        who                       Update Details:
 2009-06-04    slipa/wdavis  First version, modified from the 3D_PDK3.0 
                             for the MITLL 3D technology.
 2011-07-28    wdavis        Updated for release 1.1 of the kit

***** Please send all questions and comments to! *****


I.      Introduction
II.     Layer Cross-Reference
III.    Through-Silicon Vias
IV.     Parameterized Cells
V.      Example Layout
VI.     Display Options and Other Menu Options
VII.    Compiling Variants of this Kit

I.    Introduction

The FreePDK3D45 is a free, open source design kit compiler for stacked
dies (i.e. 3D-ICs) in a predictive 45nm technology, made possible
through the support of the Semiconductor Research Corporation.  The
kit as downloaded represents a five-tier stack of the FreePDK45
predictive technology and includes the files needed to compile other

Unlike the FreePDK45, which is intended for VLSI education, this kit
is intended for use in demonstrating and debugging new
OpenAccess-based design tools for 3D-ICs.  As such, this kit contains
the basics of what is needed to perform schematic entry, SPICE
simulation, layout, DRC, and LVS checks.  Many of the features of the
single-tier FreePDK45 are not included with this kit, such as
parasitic extraction, lithography simulation, and some of the more
complex design rules (like Antenna rules).

This document contains notes on the particulars of how 3D stacked
versions of the FreePDK45 were created.  It it not intended to be a
complete manual for the PDK, but rather a list of caveats that must be
considered when applying the FreePDK45 design flows to 3D chip stacks.

The design flow assumes the stackup included in the file
$PDK_DIR/ncsu_basekit/doc/Stackup.png, which is described in more
detail at  
We assume that Tier 1(A) will be "face up" and Tiers 2(B) through 5(E)
will be "face down."

The technology file includes 5 simultaneous Tiers allowing the
designer to maintain a complete 3D conception of his design.  Tiers
1(A) through 5(E) are provided for implementation of a complete 3D
design.  The layer names associated with these Tiers use alphabetic
suffixes.  Thus, the third-layer metal on Tier 2(B) is metal3_B.

This manual and the FreePDK45_Manual.txt are intended as introductions
to the kit, but they are by no means comprehensive.  Please see the
FreePDK Wiki for complete documentation:

II.   Layer Cross-Reference

Layers 1-34 in this kit are basically the same as with the FreePDK45.
These layers are assumed to be "tier non-specific", meaning that they
are not assumed to be on any tier.  These layers are not checked by
the Calibre DRC or LVS rules.  They are purely for convenience
when importing GDS, LEF, and DEF files.  The file 
$PDK_DIR/ncsu_basekit/techfile/techdefs.txt contains the complete
list of "tier non-specific" layers.  This file is used to compile the
technology files for Ciranova Pycell and Cadence Virtuoso.

The tier-specific layer numbers are determined by adding an offset for
that tier.  The tier-specific layer name can be determined by
appending a suffix for that tier.  The offsets and suffixes are given

Tier Offset Suffix
---- ------ ------
1(A)  300    _A
2(B)  600    _B
3(C)  900    _C
4(D) 1200    _D
5(E) 1500    _E

For those unfamiliar with Ciranova Pycell techfiles, please see the 
layerMapping() section of the file 
for the complete list of layer names.

III.  Through-Silicon Vias

All vias in this kit are Open-Access standard-vias, with the execption of
a few custom vias, as described in FreePDK45_Manual.txt.  Most vias are 
self-explanatory, following the same naming scheme as with the FreePDK45, 
but with an _A or _B suffix to denote which tier they are on.  Vias without
a suffix are assumed to be tier-non-specific.

The vias that will need some explanation are the "Through-Silicon
Vias" (TSVs), also sometimes called "Through-Stack Vias".  The metal
cross section diagram in $PDK_DIR/ncsu_basekit/doc/Stackup.png and illustrates how
a TSV from tier A to tier B is created by assuming a "Top Metal" layer
(TM) for each tier and a via from M10 to the top-metal (using a
special "up" via cut-layer called VUP).  A connection is made by
bonding two top-metal shapes face-to face.

Similarly, a back-metal (BM) is assumed to be patterned on the back of
the substrate.  A special "down" via cut-layer (VDN) is used for
connection to the back-metal.  Although not illustrated in the figure,
a fact-to-back TSV would be implemented by bonding top-metal to back-metal.

In the event that a foundry wants to create a large via through the entire 
tier, a special "through-tier" via cut-layer (VTT) has been added.  This 
cut layer may not be necessary, but many researchers have proposed that
they can be useful for such tasks as heat-removal.

From a user perspective, the standard vias TM_M10 and M1_BM have been
created to allow connection to top-metal and back-metal on any tier.
Users can create TSVs by using the appropriate combination of
tier-specific standard vias.  For example, a connection from tier A to
tier B is accomplished with a combination of TM_M10_A and TM_M10_B.  A
connection off-chip is accomplished with M1_BM_B.  This approach is
somewhat confusing, but it allows this kit to compile other
tier-stacks with minimal effort.

Finally, special vias have been added to handle the VTT cuts.  These
vias are called TM_A_BM_B, BM_B_BM_C, BM_C_BM_D, and BM_D_BM_E.  These
vias are handled as a special case by our compiler.

IV.  Parameterized Cells

Although this kit was compiled with Ciranova Pycell and can support
Pycell P-Cells, P-cells are not included with this kit.  It is assumed
that this kit will be used to help debug new, 3D-IC-enabled,
OpenAccess-based tools, rather than to perfrom custom layout in 3D-IC
technologies.  We will investigate the possibility of including
P-cells as new tools become available.

V.   Example Layouts

The $PDK_DIR/examples directory contains an example library LVS_test 
with sample cells.

  LVS_test - Contains INVS_test, an example of an inverter chain 
               in five tiers.
  DRC_test - Contains two example layouts of designs that fail and
               pass the TSV density design rule.

Further example layout can be generated quickly by using the
standard-cells in the FreePDK45 or the Nangate Open Cell Library.
Both of these libraries are layer-compatible with this kit.  Layout
can be moved between tiers with the "Move figures between Tiers"
option in the 3DIC menu.

VI.  Display Options and Other Menu Options

This Kit offers the ability to change tier visibility, in order to
help visualize 3D Designs.  The is done with the following items from
the "3DIC" Menu in Virtuoso:

         View Tier A
         View Tier B
         View Tier C
         View Tier D
         View Tier E
         View All Tiers

These menu options allow the user to view only one tier at a time or
to see all tiers simultaneously.  For example, choosing "View Tier A"
will make all layers in tiers B through E invisible and non-selectable in
the Layer Selection Window (LSW).  Choosing "View All Tiers" returns
to the default.

These menu options basically load the LSW SKILL commands from the
files (named in the ncsu_basekit/skill/display/
directory.  Modify these files if you want to set your own options.

In addition to these display options, a menu option called "Move figures
between Tiers" is available to help you to migrate a design done on one
Tier to another Tier.  Its use is self-explanatory.

VII.    Compiling Variants of this Kit

Because 3D-IC technologies are very diverse, it is likely that this
kit will need to be modified to represent the particulars of a desired
stacking technology.  The first step in such modification should be to
create a new graphic to illustrate the stack.  The file
$PDK_DIR/ncsu_basekit/doc/Stackup.vsd provides a Microsoft Visio file
that can be freely modified and distributed to describe new stacks.
For those without access to Microsoft Visio, a PNG image is also

The stackup graphic shows the additional "Stack Technology Layers"
that are added to the top and bottom of a traditional wafer technology
(such as the FreePDK45).  Each instance of a wafer technology and its
associated stacking layers above and below are considered to be a
"tier" by this kit.  This approach allows a reduction in the number of
required layer names.  Five new layer names are used, as described in
the "Through-Silicon Vias" section above.  It is assumed that most
users will want to modify the stack-technology layers and not the
wafer technology layers.

== Compiling The Technology Library ==

The technology library NCSU_TechLib_FreePDK3D45 must be re-compiled
for the following changes:
  - Adding or removing tiers
  - Adding or removing layers
  - Modifying the standard via definitions

If you need to make any of these changes, then note the following:
  - Refer to the following web-page for instructions on how to
    compile a new technology library for the single-tier FreePDK45:
  - This kit uses a similar "" script to compile the 
    technology.  The primary difference is that another script is 
    called, which is defined in
  - The script generates both the Pycell "" 
    file and Virtuoso "" files used by
  - The script also generates the file,
    which is current modified by hand to produce the files in the
    $PDK_DIR/ncsu_basekit/skill/display directory, which enable
    selectively displaying tiers.

== Modifying the Techfiles ==

Modification of the tiers and layers can be accomplished by modifying
the script until the desired kit is achieved.  We expect
that the existing layers and tiers are overkill for most applicatoins,
and so we will not go into greater detail on layer/tier modification
in this document.

Because the standard-via definitions are rather complex, the techfile
code for these vias is currently hand-authored and not generated by
the script.  The file
$PDK_DIR/ncsu_basekit/techfile/cds_others_5.txt currently contains the
"viaDef" section of the Virtuoso technology file and is concatenated
into  We recommend modifying this file and
re-compiling with to produce new via behavior.  Note that
the file "cds_others_2.txt" is the file we use to generate 2-tier
variants of this kit.

== Modifying the Calibre Rules ==

DRC and LVS rules are not modified by the script described
above.  Rather, the DRC and LVS rules have been compiled with a script
developed by MIT Lincoln Laboratories.  This script can be found at
the following location:

Use this script to generate multi-tier versions of a single-tier
rule file with the following command:

./ -infile [rulefile] -config FreePDK3D45.cfg -outpath .

This approach is used on the following rule-files to produce the
indicated multi-tier rule-files in the same directory:
 - FreePDK45_master_top.rules  => 3D_FreePDK45_master_top.rules
 - FreePDK45_drc.rules         => 3D_FreePDK45_drc.rules
 - FreePDK45_lvs.rules         => 3D_FreePDK45_lvs.rules

The file 3D_FreePDK45_density.rules contains the TSV density rules, 
which have not yet been incorporated in the the perl-script.

Finally, the files 3D_FreePDK45_calibreDRC.rules and
3D_FreePDK45_calibreLVS.rules are the top-level files that
reference the four "3D_*" files mentioned above.

The most-likely change that we imagine users wanting to make will be
the LVS connections through the stack layers.  These connections are
defined with the SVRF "connect" commands located at the bottom of the
3D_FreePDK45_calibreLVS.rules file.  Note that modifying these
connections does not require re-generation of the multi-tier versions
of the wafer-technology rules.

Happy modifying!

***** Please send all questions and comments to! *****