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Extraction is the process by which electrical connectivity and circuit elements are derived from the drawn layout. The CDK currently extracts the following circuit elements: [NP]MOSFETs, NPN BJTs, diodes, capacitors, and poly/elec/nwell resistors. (Parasitic resistance extraction is not supported.)

The following is a list of recognized extraction switches followed by a brief explanation. Switches marked with an asterisk (*) affect the "layout" view, not the "extracted" view.

  • Convert_[np]active_to_active (*) Convert [np]active to active
  • Convert_active_to_[np]active (*) In an nwell process, convert active surrounded by nselect to nactive, otherwise to pactive. In a pwell process, convert active surrounded by pselect to pactive, otherwise to nactive.
  • Create_[np]select_around_[np]active (*) For [np]active shapes, create an enclosing shape of [np]select
  • Create_select_around_field_poly (*) In the TSMC 0.25um process, all field poly must be enclosed by either n or p select. This switch creates this enclosure around all poly that is not already enclosed by select. Note that MOSIS now performs this step for you, so you shouldn't need to use this switch!
  • Extract_parasitic_caps Extract interconnect parasitic capacitors. Capacitors below the value defined by NCSU_parasiticCapIgnoreThreshold (in local/skill/globalData.il) are ignored. To change this value, set NCSU_parasiticCapIgnoreThreshold = x, where x is the value in Farads.
  • Keep_labels_in_extracted_view Migrate text labels from layout to extracted view (in addition to naming the nets)
  • No_parameters Do not assign values of as,ad,ps,pd to FETs or values to capacitors. Do not assign model names to FETs.


MOSFET source/drains are created by surrounding an "active" shape with either "nselect" or "pselect", depending on the desired MOS flavor. The gate is "poly" over active. Depending on the MOS flavor and process, the active area might need to be enclosed in a well. (Eg, PFETs need to be enclosed by "nwell" in an nwell process.) Variations include using "elec" for the gate (when allowed by the process) and "[np]active" for active, which gives better visual feedback than just active everywhere.

The four-terminal MOSFETs [np]mos4 from the NCSU_Analog_Parts library, not the three-terminal devices, are placed in the extracted view.

For processes that support them, high-voltage devices can be instantiated with the [np]mos_hv and [np]mos4_hv cells. They are made in layout just as a normal device but with "tactive" surrounding the active.


Vertical BJTs are extracted. The collector is "cactive" enclosed by "nselect." The emitter and base are "nselect" and "pselect" respectively, both enclosed by "pbase." All three terminals are further enclosed by "nwell" (which is actually the collector). Since different models are generally used for different geometry NPNs, unlike scalable MOSFET models, the rules do not extract any information about the NPN other than node names for the three terminals. Thus, to simulate, the user must edit the netlist and insert the correct NPN model name for each device.


If the Extract_resistors switch is on, the following structures are extracted as resistors:

  • "poly" or "elec" enclosed by "res_id"
  • "poly" enclosed by "sblock"
  • "elec" enclosed by "highres"
  • "nwell" enclosed by "res_id"

Not every process has all these layers; as of now, for example, only the AMI C5N 0.6um (drawn) process has "highres." For purposes of calculating resistance values, only the area of poly/elec/nwell actually enclosed by res_id/sblock/highres is considered.

Sheet resistance values are in $cdk_dir/techfile/layerDefinitions.tf. To change these values in existing libraries:

  • In the CIW, use the "Technology File -> Dump..." menu entry to dump the "layerDefinitions" class of the desired tech library to a file.
  1. Go to the techLayerProperties section (it's probably at the bottom of the file) and either change the resistance value or add a line of the form:( sheetResistance layer value ) where layer is the layer name (e.g., nwell, poly) and value is the sheet resistance in Ohms/square. E.g.:( sheetResistance nwell 1191 )
  • In the CIW, use the "Technology File -> Load..." menu entry to load the file you just edited (select the "Merge" option).
  • In the CIW, use the "Technology File -> Save..." menu entry to

save the technology library you just modified.


The following structures, "intentional" capacitors, are always extracted as capacitors:

  • "metal1"/"poly" overlap enclosed by "cap_id"
  • "metal2"/"metal1" overlap enclosed by "cap_id"
  • "metal3"/"metal2" overlap enclosed by "cap_id"
  • "metal4"/"metal3" overlap enclosed by "cap_id"
  • "metal5"/"metal4" overlap enclosed by "cap_id"
  • "metalcap"/"metal5" overlap
  • "poly"/"active" overlap enclosed by "cwell" (thin-oxide capacitor)
  • "poly"/"polycap" overlap

If the Extract_parasitic_caps switch is on, parasitic capacitors are extracted for all interconnect layers.

Capacitance values are in $cdk_dir/techfile/layerDefinitions.tf. See the section on resistors for instructions on how to change the values for existing libraries.