Design Rule Checking

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Design Rule Checking

N.B. - This page is out of date (SL 2006-02-27)

Design Rule Checking (DRC) is the process by which a layout is checked to see if it complies with all the rules set in place by the IC foundry to ensure an acceptable level of manufacturability. All the SCMOS design rules as described in the MOSIS SCMOS User's Manual are implemented. The CDK implements the "submicron" variant of the rules (SCMOS_SUBM).

The following DRC switches are recognized:

  • areaPads? -Use different pad/glass rules for area-array I/O (not MOSIS supported!)

--Slipa 12:07, 27 February 2006 (EST)