Difference between revisions of "Tutorial:ASIC Design Tutorials"

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(Tutorial2: Introduction to Methodology for Design Analysis)
(Updated Tut1_Synth and doc files for Tutorial 1)
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== Tutorial1: Introduction to Simulation and Synthesis ==
 
== Tutorial1: Introduction to Simulation and Synthesis ==
'''The tutorial can be downloaded at:'''  [http://www.ece.ncsu.edu/asic/share/Tutorial1.pdf pdf]  [http://www.ece.ncsu.edu/asic/share/Tutorial1.doc doc]      '''(last modified Jan 31, 2008)'''
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'''The tutorial can be downloaded at:'''  [http://www.ece.ncsu.edu/asic/share/2011/Tutorial1.pdf pdf]  [http://www.ece.ncsu.edu/asic/share/2011/Tutorial1.doc doc]      '''(last modified Jan 26, 2011)'''
  
 
This tutorial provides a brief introduction to the tools that are going to be used for designing of ASIC systems. To this end, we will be using Mentor Graphics Modelsim for Simulation and the Synopsys Design Compiler environment for Synthesis. It is interesting to note that the Modelsim tool enables compilation of multiple design/verification/modeling units (each of which might be in a different language) into a common library (called the working library) and a common design representation. This enables each individual unit of the entire simulation to be compiled independantly and incremental compilation to be performed. The following files come with this tutorial (please download and store per the instructions provided within the tutorials):
 
This tutorial provides a brief introduction to the tools that are going to be used for designing of ASIC systems. To this end, we will be using Mentor Graphics Modelsim for Simulation and the Synopsys Design Compiler environment for Synthesis. It is interesting to note that the Modelsim tool enables compilation of multiple design/verification/modeling units (each of which might be in a different language) into a common library (called the working library) and a common design representation. This enables each individual unit of the entire simulation to be compiled independantly and incremental compilation to be performed. The following files come with this tutorial (please download and store per the instructions provided within the tutorials):
  
 
* '''Files for PartA: Simulation''':  
 
* '''Files for PartA: Simulation''':  
**[http://www.ece.ncsu.edu/asic/share/Tut1_Sim/counter.v counter.v]  
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**[http://www.ece.ncsu.edu/asic/share/2011/Tut1_Sim/counter.v counter.v]  
**[http://www.ece.ncsu.edu/asic/share/Tut1_Sim/test.v test.v]  
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**[http://www.ece.ncsu.edu/asic/share/2011/Tut1_Sim/test.v test.v]  
**[http://www.ece.ncsu.edu/asic/share/Tut1_Sim/modelsim.ini modelsim.ini]  
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**[http://www.ece.ncsu.edu/asic/share/2011/Tut1_Sim/modelsim.ini modelsim.ini]  
  
 
* '''Files for PartB: Synthesis''':  
 
* '''Files for PartB: Synthesis''':  
**[http://www.ece.ncsu.edu/asic/share/Tut1_Synth/.synopsys_dc.setup .synopsys_dc.setup]  
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**[http://www.ece.ncsu.edu/asic/share/2011/Tut1_Synth/.synopsys_dc.setup .synopsys_dc.setup]  
**[http://www.ece.ncsu.edu/asic/share/Tut1_Synth/setup.tcl setup.tcl]  
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**[http://www.ece.ncsu.edu/asic/share/2011/Tut1_Synth/setup.tcl setup.tcl]  
**[http://www.ece.ncsu.edu/asic/share/Tut1_Synth/read.tcl read.tcl]  
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**[http://www.ece.ncsu.edu/asic/share/2011/Tut1_Synth/read.tcl read.tcl]  
**[http://www.ece.ncsu.edu/asic/share/Tut1_Synth/Constraints.tcl Constraints.tcl]  
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**[http://www.ece.ncsu.edu/asic/share/2011/Tut1_Synth/Constraints.tcl Constraints.tcl]  
**[http://www.ece.ncsu.edu/asic/share/Tut1_Synth/CompileAnalyze.tcl CompileAnalyze.tcl]
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**[http://www.ece.ncsu.edu/asic/share/2011/Tut1_Synth/CompileAnalyze.tcl CompileAnalyze.tcl]
  
 
== Tutorial2: Introduction to Methodology for Design Analysis ==
 
== Tutorial2: Introduction to Methodology for Design Analysis ==

Revision as of 10:09, 26 January 2011

INTRODUCTION

The tutorials in this section are used in ECE 520 ASIC Design. This course provides deals with design of complex digital systems, their synthesis and their verification. To this end, students are given an introduction to the necessary CAD tools, particularly for Simulation and Synthesis of such systems. The following Tutorials progressively build up the knowledge base for the above


Tutorial1: Introduction to Simulation and Synthesis

The tutorial can be downloaded at: pdf doc (last modified Jan 26, 2011)

This tutorial provides a brief introduction to the tools that are going to be used for designing of ASIC systems. To this end, we will be using Mentor Graphics Modelsim for Simulation and the Synopsys Design Compiler environment for Synthesis. It is interesting to note that the Modelsim tool enables compilation of multiple design/verification/modeling units (each of which might be in a different language) into a common library (called the working library) and a common design representation. This enables each individual unit of the entire simulation to be compiled independantly and incremental compilation to be performed. The following files come with this tutorial (please download and store per the instructions provided within the tutorials):

Tutorial2: Introduction to Methodology for Design Analysis

The tutorial can be downloaded at: pdf doc (last modified Feb 25, 2008)

Accompanying Presentation on Tutorial2: pdf

This tutorial provides an example based step-by-step introduction to the methodology that is going to be followed for the analysis of designs. The aim is to provide a realistic power and timing value for the design by running the design through a prototyping flow that would provide a layout based view of the circuit performance. This requires that you start off with the netlist that results from Synthesis as explained in Tutorial 1. This Tutorial also provides information on the directory structure that is going to be followed for organization of your work. The main logical steps of this tutorial are (starting with a synthesized netlist per Tutorial 1):

  • The PAD_Flow.pl script that comes with this tutorial is run to create the Standard Parasitic Exchange Format (SPEF) file. This file captures the capacitance and resistance of the wiring network in your design. This is explained in Section 5.a of the tutorial.
  • The testbench is modified to be able to capture the toggling statistics of the nets in the design. This information is captured in a Switching Activity Interchange Format (SAIF) file. The method for doing this is explained in Section 5.b. THIS IS A MANUAL STEP.
  • The PAD_Flow.pl script is run to create final power and delay information for the design using the SAIF and SPEF files from the previous steps. This is explained in Section 5.c of the tutorial.


The files that are needed for this tutorial can be found at(please download and store per the instructions provided within the tutorial):

  • PAD_Flow.pl The automation script for analysis.
  • counter.v The design that we are working with. It is a larger version of the counter from Tutorial 1.
  • test.v The initial testbench for the Design Under Test.
  • test_switching.v The testbench with commands for SAIF creation that will be used in Section 5.b.
  • modelsim.ini Copy to ./SIMULATION/run_f and ./SIMULATION/run_s after setup
  • Library_fwd.saif Copy to ./SIMULATION/run_f after setup
  • designenv.tcl Copy to ./SYNTH/run_f after setup

Tutorial3: Complex Design Example and Memory Generator

The tutorial can be downloaded at: pdf doc (last modified April 4, 2008)


This tutorial provides a the reasoning and steps to be followed in designing more complex systems. Thoughts on design thinking about IO requirements, to hierarchy to separation of control and data paths is explained. The creation of SRAMs using Memory Generators is explained and the incorporation of Memory Models in the timing and power analysis of a design is shown.

The files that are needed for this tutorial can be found at(please download and store per the instructions provided within the tutorial):

  • CreateModel.pl The Memory Generator script. (UPDATED: April 4)
  • Engine.v The search engine that forms the core of the datapath.
  • Controller.v The Controller that manages the operation of the datapath.
  • top_with_mem.v The file that integrates top.v and the Memory Model.
  • top.v The top level integration of the controller and the engines.
  • test.v The initial testbench for the Design Under Test.
  • test_switching.v The testbench with commands for SAIF creation.
  • memdata.txt The 8 bit memory image that will be loaded into the memory array using $readmemh().

UPDATED: April11: The following document explains the means of performing the power analysis with multiple memories can be downloaded from TwoMemories.pdf. The document uses two memories to illustrate the method but this can easily be extended to multiple memories. The necessary files for this document are:

  • top_with_2mem.v The file that integrates top.v and two memories instead of just one.


Tutorial4: FPGA Design Flow using Xilinx ISE Environment

The tutorial can be downloaded at: pdf doc This tutorial provides a brief overview of how to design hardware systems for FPGAs. It assumes knowledge of Verilog, and will show you how to take an existing Verilog design, and target it to a specific FPGA. This is a useful skill in industry because many designs are prototyped using FPGAs due to quick time-to-market and low initial cost. This tutorial will cover how to access the Xilinx software at NC State, then will cover Design Input, Synthesis, Constraining, Implementation and Bitstream Creation.

The files that are needed for this tutorial can be found at(please download and store per the instructions provided within the tutorial):