Tutorial:Questa SystemC Tutorial
From NCSU EDA Wiki
INTRODUCTION
This tutorial deals with the provision of a typical SystemC code structure and its simulation using Questa/Modelsim from Mentor Graphics
Tutorial: SystemC: Introduction, Simulation using Questa/Modelsim and Transaction Level Models
The tutorial can be downloaded at: pdf doc (last modified July 7, 2008)
The aim of this tutorial is to understand the basic language constructs of SystemC. These language fundamentals are going to be used in the description of a simple FIR filter design. The FIR filter consists of a producer that generates data that is needed as an input and an accelerator that computes the FIR result. The two units communicate with each other over nets and also share common input signals for clock, reset and enable. Additionally, we will provide an example of a Transaction Level Model (TLM) of the above system. This is done by introducing the need for a FIFO between the accelerator and the producer to deal with issues of the sub-modules working at different rates. This connectivity is achieved by the use of a sc_fifo transaction level channel and its interfaces.
The necessary files for this tutorial
FILES FOR PART 1
Please download as directed in the tutorial
- Header Files: producer.h accelerator.h Top.h
- Source Files: producer.cc accelerator.cc Test_Top.cc
- Definition Header: defs.h
- Modelsim Initialization File: modelsim.ini
- Example Modelsim .do file: compile.do: This assumes that the source files are within "../Source/PartC/" and you can call the .do file within the vsim environment as
VSIM#> do compile.do
FILES FOR PART 2
Please download as directed in the tutorial
- Header Files: producer.h accelerator.h Top.h
- Source Files: producer.cc accelerator.cc Test_Top.cc
- Definition Header: defs.h
- Example Modelsim .do file: compile.do:
