Tutorial:Lithography Simulation
From NCSU EDA Wiki
In this tutorial you will create a layout, analyze it using Calibre's Litho-Friendly Design package, and use layout techniques to improve your yield.
Contents |
Set Up Your Environment
In order to start this tutorial, execute the following commands as outlined in the LFD setup page.
add calibre20073 add_cadence2008 add_freepdk45 virtuoso &
Create a New Layout
A a 3-input nand gate layout has been provided for your as a starting point for this tutorial. Copy this cell into your own private library so that you can modify it. The layout can be found in a library called tut4cells. In order to see this library, add the following line to the cds.lib file in the directory where you started Cadence (should be a single line):
DEFINE tut4cells /afs/eos.ncsu.edu/lockers/research/ece/wdavis/tech/ece546/tut4cells
Next choose View->Refresh in the library manager window. You should see the tut4cells library appear.
Run LFD on Your Layout
You can run LFD by selecting Calibre->Run DRC from the menu bar, which brings up the Calibre Interactive window. Load the LFD runset file by selecting File->Load Runset from this window, and typing in ".runset.calibre.lfd". (Note: If you are prompted about whether or not to save the current runset file, I would click "no".) Then click "Run DRC."
Open the process variability bands results database in the RVE window by clicking File->Open Database... and selecting the file lfd_pvband.rdb.
You can highlight the worst case metal pvbands by right-clicking on "Check lfd_pvb_metal1_p3" and selecting "Highlight Cluster." Then you can also highlight the worst case poly pvbands by checking "Check lfd_pvb_poly_p3". Your layout should now look like this:
Note that, in some regions, especially around jogs, metal lines have PV bands which are significantly narrower than the drawn width. This can cause higher resistance in the lines, which is not desirable. In this case, we do not want metal lines to have PV bands narrower than 47.5nm. These regions can be observed from the RVE window by clicking File->Open Database... and selecting the file lfd_error.rdb. Then you can highlight the errors by right-clicking on "Check lfd_metal1_MWC_p3" and selecting "Highlight Cluster." These rectangle regions are the ones where metal1 have a width smaller than 47.5nm. Your layout should now look like this:
The lfd_error.rdb file will serve as our main evidence that the design has "passed" the LFD rule check and is good for fabrication, even if the layout fails a normal DRC check. The LFD simulation gives us a more accurate idea of the variation that is likely to occur during fabrication, but it's impractical to use this type of simulation for the entire chip, because it would take too much time. Therefore, LFD simulations are normally performed on cells that occur very often in the design and are critical to the overall performance, such as an SRAM bitcell.
Since the lfd_error.rdb file is so important, open it up in a text editor to see what it looks like. You should notice from the Calibre - DRC RVE window that the rule that's failing is called "lfd_metal1_MWC_p3". Scan forward in the file to the line that contains this text, and you should see the following:
lfd_metal1_MWC_p3 9 9 3 Oct 30 14:44:25 2009
The first line gives the name of the rule, and the "9" that begins the second line shows how many errors there are that need to be fixed. It's inconvenient to have to check for errors this way, but until we learn better how to write Calibre LFD rules, this is how we need to do it.
Fixing the LFD Errors
Here are the ways that we can fix these errors:
- In general, what makes lithography at these small dimensions so hard is that we have drawn right angles, but it's easier to print smooth curves. The mask-generation tools are doing their best to give us what we want, but they have limits. We can make the mask-generation task easier if we modify the layout to have smoother curves. That way, it's easier for the tools, because they can don't have to work so hard to give us right-angles. Look in the figure below and see how metal1 pieces 15nm wide and 50nm long have been put around the right angles, in order to make the edges smoother.
- In other cases, we simply need to tell the mask-generation tools to try harder to print certain features. Note in the figure below the "line end-caps" that have been added to some of the metal1 edges (70nm wide, 150nm long). These features will tell the tools to try harder to maintain the width of the lines around the edges.
- Finally, in some cases, there's nothing you can do except make the metail line wider. Notice that some metal lines have been widened to 70nm around the jogs.
The fixed layout is shown below:
You can now run LFD on your updated layout and check the lfd_error.rdb file as mentioned above. After the corrections, your layout should be LFD clean which means you should not have any LFD minimum width violation for metal1. Looking in the file, you can scan forward to the previous error and see something like the follwoing:
lfd_metal1_MWC_p3 0 0 3 Oct 31 10:30:59 2009
The "0" that begins the last line indicates that there are no errors. Finally you can highlight the pvbands as mentioned previously. Your layout with pvbands becomes as follows:
After the updates we not only solved the problems but also reduced the variations through the metal1 pvbands. If you look at the pvbands of the first and updated layout, you see that the latter one has more straight pvbands, which means it is less susceptible to resistance variations. For the purposes of this course, however, a layout will be considered "correct" if it has no error markers in the lfd_error.rdb file AND if it passes a normal DRC check for the layers not included in the LFD check. Note that the LFD check is considering only the layers active, contact, poly, and metal1, which have the smallest features in this technology.
Congratulations! You are done!
