NCSU CDK overview

From NCSU EDA Wiki

NCSU CDK Overview

The NCSU CDK focuses on providing the means to do full-custom CMOS IC design (SCMOS design rules) through MOSIS, including schematic entry, Verilog digital simulation, analog circuit simulation, layout DRC checking and device extraction, and mask generation. It requires Cadence 4.4 or higher and is not backward compatible with 4.3.x. All SKILL code is available as source.

The tools used in the kit are Virtuoso, Composer, Analog Artist, Virtuoso-XL and Diva.

What it is...

In particular, the kit features:

• support for all MOSIS processes which support the SCMOS rules, including process-dependent layers, e.g., pbase for NPNs
• layermaps for MOSIS CIF/GDSII import/export
• Diva verification: DRC (all rules from the MOSIS SCMOS User's Manual 8.0 excluding some DEEP rules and wide-metal spacing rules), extraction (MOSFETs, high-voltage MOSFETs, cwell/{m1,elec,polycap}-poly/inter-metal/metalcap/parasitic capacitors, vertical NPN BJTs, diodes, resistors), and LVS
• Composer with interface to:
  • HSPICE/Spectre through Analog Artist, with MOSIS-provided transistor models in place
  • Verilog with technology-independent parts
• technology-independent libraries for analog (eg, RLC, transistors) and digital (eg, gates) parts. These parts have SKILL code hooked in to enforce sizing and grid rules (eg, minimum width/length, half-lambda grid), automatic transistor model selection depending on technology, and drain/source area/perimeter estimation.
• technology libraries (ie, one library for every MOSIS SCMOS process) with parameterized layout cells setup for both manual use and layout synthesis via Virtuoso-XL
• MOSIS wirebond pads (HP 0.6um; AMI 0.6um; TSMC 0.40um)
• various user-friendly GUI enhancements
  • simplified library creation and technology file attachment for MOSIS technologies
  • click on any object to print info about it in the CIW
  • enhanced label creation (Virtuoso)
  • align layout objects (Virtuoso)
  • Perl/Tk program to easily convert 1's and 0's into SPICE pwl and pulse sources,
  • create a "publication-quality" schematic from a working schematic
• documentation of all customizations in HTML

and what it isn't...

A few big things that the kit does not expressly do:

• Place and Route
• provide a standard cell layout library
• digital timing analysis
• parasitic resistance extraction

--Slipa 16:29, 28 February 2006 (EST)